Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.

Abstract: An antenna array includes a glass plate, a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a feeding network. The glass plate has a first surface and a second surface which are opposite to each other. The ground element is disposed on the second surface of the glass plate. The feeding network has a feeding port. The feeding network is coupled to the first radiation element, the second radiation element, the third radiation element, and the fourth radiation element. The first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the feeding network are disposed on the first surface of the glass plate.

Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: An over-current protection device includes a resistor element, an outer electrode, and an encapsulation layer. The resistor element has a first insulation layer, a first electrically conductive layer, a PTC material layer, a second electrically conductive layer and a second insulation layer stacked sequentially from bottom to top. The first insulation layer has a bottom surface and a first sidewall adjoining the bottom surface. The outer electrode has a first electrode and a second electrode disposed on the bottom surface. The first and second electrodes are electrically connected to the first conductive layer through the first and second vias, respectively. The encapsulation layer covers the first sidewall of the first insulation layer and extends to a part of the bottom surface, thereby forming a first perimeter on the bottom surface of the first insulation layer. The first and second electrodes are located inside the first perimeter.

Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: A package structure includes a carrier substrate and a die. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The semiconductor substrate is located between the conductive posts and the carrier substrate.

Abstract: Disclosed in embodiments of the present disclosure are a communication terminal, a communication system and an audio information processing method, the communication terminal includes a sound reception assembly and a basic communication module, wherein the basic communication module of the communication terminal receives second pickup audio information in a wireless manner, such that the communication terminal acquires returned audio information according to first pickup audio information generated by the communication terminal and the received second pickup audio information, and transmits outwards the returned audio information. Therefore, the technical solution in the embodiments of the present disclosure may realize synchronous sound reception of a plurality of wireless sound reception apparatuses or wireless sound reception components, and may satisfy a requirement for multiple people to use, thereby achieving a good sound reception effect.

Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.

Abstract: A semiconductor device includes a substrate and two fins protruding from the substrate. Each fin includes two source/drain (S/D) regions and a channel region. Each fin includes a top surface that remains flat across the S/D regions and the channel region. The semiconductor device also includes a gate stack engaging each fin at the respective channel region, a first dielectric layer on sidewalls of the gate stack, a first epitaxial layer over top and sidewall surfaces of the S/D regions of the two fins, and a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer.

Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.

Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.

Abstract: The present invention provides a micro-action ratchet wrench. a wrench has a main hole arranged thereon and a first and a second arc surfaces recessed in the wall surface of the main hole for correspondingly forming the first and second chambers, so that the centerlines of the first and second chambers intersect with the center of the main hole to maintain a set angle. The main hole is coupled with a ratchet. The ratchet has an outer connection portion and an outer teeth portion. The first and second chambers are correspondingly equipped with the first and second detents and the first and second springs. The first and second detents are provided with pawls, the first and second springs actuate the corresponding first and second detents, so that the pawls of the first and second detents can differentially engage the outer teeth portion of the ratchet through the set angle configuration.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: A method for detecting defects in a semiconductor structure is provided. The method includes the following operations. A semiconductor structure having a plurality of conductive structures is received. An electron beam inspection operation is performed on the plurality of conductive structures of the semiconductor structure to obtain an inspection data, wherein a pulsed electron beam utilized in the electron beam inspection operation is selected from the group consisting of a nanosecond pulsed beam, a picosecond pulsed beam, and a femtosecond pulsed beam. A first conductive structure having a non-open defect is identified from the inspection data. A method for classifying semiconductor structure is also provided.

Abstract: Persistent storage contains a parent table and one or more child tables, the parent table containing: a class field specifying types, and one or more filter fields. One or more processors may: receive a first request to read first information of a first type for a first entity; determine that, in a first entry of the parent table for the first entity, the first type is specified in the class field; obtain the first information from a child table associated with the first type; receive a second request to read second information of a second type for a second entity; determine that, in a second entry of the parent table for the second entity, the second type is indicated as present by a filter field that is associated with the second type; and obtain the second information from a set of additional fields in the second entry.

Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: A method and a device for scheduling charging. The method includes the following steps: multiple charging records are collected; multiple charging time data of the charging records of which charging duration is within a predetermined time range is extracted from the collected charging records; and the charging time data is analyzed by using a way of weight point to obtain a suggestion charging period.

Abstract: A display device including a display module and a backlight module is provided. The display module has a display region. The backlight module is overlapped with the display module and includes a plurality of light emitting diodes. The plurality of light emitting diodes form a light emitting region. The light emitting region is overlapped with the display region, and an area of the light emitting region is larger than an area of the display region.