Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

Abstract: A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.

Abstract: A method for fabricating a flash memory cell is provided. After an ONO dielectric layer is formed on a first conductive layer over a tunnel oxide layer, a second conductive layer is formed on the ONO dielectric layer. Then, patterning the second conductive layer to form a periphery region comprising an exposed portion of a semiconductor substrate and a memory cell region comprising the left second conductive layer. During the present process, the ONO dielectric layer is protected from being exposed in various solvents and gases with the second conductive layer. Thus, a flash memory cell with a high-quality ONO gate dielectric layer, without increasing complexity of the process and additional masks, is obtained.

Abstract: A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.

Abstract: A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.

Abstract: A polysilicon self-alignment contact and a polysilicon common source line. A cell array formed on a semiconductor substrate has a second cell adjacent to a first cell in a Y-axis orientation, and a third cell adjacent to the first cell in an X-axis orientation. Each cell comprises a first gate structure and a second gate structure, a source region formed in the semiconductor substrate adjacent to the first gate structure and the second gate structure, and an opening formed between the first gate structure and the second gate structure to expose the source region. A drain region is formed in the semiconductor substrate adjacent to the second gate structure of the first cell and the first gate structure of the second cell. A contact hole is formed between the first cell and the second cell to expose the drain region. A polysilicon layer is formed in the contact hole to serve as a polysilicon self-aligned contact.