Abstract: An apparatus for detecting the presence of a frequency channel is provided. The apparatus comprises an energy detection unit configured to measure receive energy over a first bandwidth and a second energy detection unit configured to measure receive energy over a second bandwidth. The apparatus further comprises a processor configured to compare the measured receive energy over the first bandwidth to a first energy threshold, to compare the measured receive energy over the second bandwidth to a second energy threshold, and to detect the presence of the frequency channel when the measured receive energies over the first and second bandwidths are above the first and second energy thresholds, respectively.

Abstract: A channel scanning order is dynamically created, modified, selectively ignored, or combinations thereof based on historical data, motion information, context information, alert message systems, network reselection, or combinations thereof. If a less preferred network has served a mobile device longer than a threshold amount of time, acquisition of the less preferred network is attempted before attempting acquisition of a more preferred network.

Abstract: The standby time of a CDMA cell phone is extended by using two receive chains to monitor the Quick Paging Channel (QPCH) when the signal-to-noise ratio falls within a predetermined range. Monitoring the QPCH saves battery power by obviating the need to monitor the general paging message unless quick paging (PI) bits are set. The QPCH is not monitored, however, in noisy environments where PI bits are incorrectly detected causing the paging message to be needlessly monitored. Power is saved by monitoring the QPCH in noisier environments without increasing the incorrect detection rate. Incorrect detection is reduced in the predetermined range by using an additional receive chain to achieve receive diversity. Although additional power is consumed by the second receive chain in the predetermined range, the power saved by not demodulating the paging message at each slot more than compensates for the additional power consumed by the second receive chain.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data.

Abstract: An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.

Abstract: Systems and methodologies are described that facilitate optimum technology selection within multi-modal configurations. A multi-mode mobile device can select and/or utilize a particular technology, system and/or configuration to provide optimal quality of service (QOS) in terms of various characteristics. For instance, an optimum technology can be selected and employed for a service request based upon performance, cost, power consumption, interference levels, and the like. The multi-modal mobile device can obtain characteristics of a plurality of technologies during idle states. The characteristics can be analyzed in order to generate a QOS table that provides relative rankings of the plurality of technologies in terms of service request type and the obtained characteristics. The QOS table can be utilized to select an optimum technology upon initiation of a service request.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: The invention provides a method for current reduction for an analog circuit in a data read-out system. First, a performance indicator, indicating a performance of the data read-out system is generated. The performance indicator is then compared with a performance threshold level to generate a switch signal. A level of a current source biasing the analog circuit is then adjusted according to the switch signal.

Abstract: A Delta-Sigma DAC and a digital to analog conversion method are provided. A FIR filter receives a shaped digital signal to generate a first current on a first output node, and a second current on a second output node. A current inverter is coupled to the second output node, outputting a reversed current having opposite polarity and identical magnitude of the second current. A current to voltage converter is coupled to the first output node and the output of current inverter, generating an analog signal according to the first and reversed currents. A first current source compensates DC offset for the first current, and a second current source compensates DC offset for the second current. The first and second current sources are implemented by NMOS.

Abstract: Variable gain amplifiers with wider linear range are provided, in which first and second loads are coupled to a power voltage, and a transconductor cell comprises first and second transistors, a gain control transistor, and first and second current sources. The first and second transistors comprise control terminals receiving a set of input signals, first terminals coupled to the first and second loads respectively, and second terminal coupled to first and second nodes respectively. The first and second current sources are coupled between the first node and a first voltage and between the second node and the first voltage respectively. The first gain control transistor is coupled between the first node and second node, receiving a gain control voltage, in which the grain control transistor has a threshold voltage lower than that of the first and second transistors.

Abstract: Methods, devices and computer program products are disclosed that allow for wireless communication devices to operate more robustly in the slotted mode of operation in the event of network system loss. Specifically, present aspects require the wireless device to move to or remain in the slotted mode of operation as opposed to immediately entering into a system determination/acquisition mode upon failing to acquire an active set pilot during a slotted wake-up. By moving to the slotted mode of operation or providing for additional slotted-wake-ups, a number of attempts at acquiring the active set pilot can be performed before declaring the system as lost, thereby allowing for fading channel conditions to prevail without the need to re-acquire the lost system or otherwise acquire another system. Since the performance of the slotted mode is less power intensive than acquiring or re-acquiring a system, a substantial power savings is realized.

Abstract: An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data.

Abstract: Embodiments include a method of signal processing in which each of a set of individual estimates of a transmitted symbol is added to a combined symbol estimate based on a relation between a signal quality value corresponding to the individual estimate and a threshold value, where the threshold value is based on a maximum among the signal quality values.

Abstract: A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result.

Abstract: A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

Abstract: The invention provides a method of gain error calibration in a pipelined analog-to-digital converter (ADC). In one embodiment, a first stage and a second stage of the pipelined ADC share a common operational amplifier. The first stage is requested to generate the stage output signal thereof according to a first correction number. The second stage is also requested to generate the stage output signal thereof according to a second correction number. A plurality of stage output values generated by stages of the pipelined ADC are collected. The stage output values are respectively correlated with the first correction number and the second correction number to estimate a first gain error estimate of the first stage and a second gain error estimate of the second stage. The first gain error estimate and the second gain error estimate are weighted to obtain a predicted gain error for gain error calibration in the first stage and the second stage.

Abstract: A Delta-Sigma DAC and a digital to analog conversion method are provided. A FIR filter receives a shaped digital signal to generate a first current on a first output node, and a second current on a second output node. A current inverter is coupled to the second output node, outputting a reversed current having opposite polarity and identical magnitude of the second current. A current to voltage converter is coupled to the first output node and the output of current inverter, generating an analog signal according to the first and reversed currents. A first current source compensates DC offset for the first current, and a second current source compensates DC offset for the second current. The first and second current sources are implemented by NMOS.

Abstract: The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value.