Abstract: An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal and a method of fabricating the active quadrature generation circuit on an integrated circuit are described. The circuit includes an input node to receive the input signal and a first transistor including a collector connected to a power supply pin. The circuit also includes a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

Abstract: An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal and a method of fabricating the active quadrature generation circuit on an integrated circuit are described. The circuit includes an input node to receive the input signal and a first transistor including a collector connected to a power supply pin. The circuit also includes a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

Abstract: A apparatus for dynamically modifying filter characteristics of a delta-sigma modulator in order to receive and transmit radio frequency signals over a wide frequency range. The system is used for wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a cellular radio architecture that employs a combination of a single circulator, programmable band-pass sampling radio frequency (RF) front-end and optimized digital baseband that is capable of supporting all current cellular wireless access protocol frequency bands.

Abstract: A apparatus for dynamically modifying filter characteristics of a delta-sigma modulator in order to receive and transmit radio frequency signals over a wide frequency range. The system is used for wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a cellular radio architecture that employs a combination of a single circulator, programmable band-pass sampling radio frequency (RF) front-end and optimized digital baseband that is capable of supporting all current cellular wireless access protocol frequency bands.

Abstract: A cellular radio architecture that includes an RF transmitter having a digital signal processor, a digital-to-analog converter (DAC) module that converts digital bits from the processor to an analog signal, a tunable bandpass filter that removes frequencies in the analog signal outside of a frequency band of interest, and a power amplifier that amplifies the filtered analog signal. The architecture also includes a calibration feedback device that receives the amplified analog signal and provides a feedback signal to the processor for calibrating the digital signal to provide amplified amplifier pre-distortion. The processor employs a noise-shaping operation to shape the analog signal from the DAC to remove quantization noise in an immediate vicinity of the signal to improve signal-to-noise ratio, performs an infinite impulse response process to lower a noise floor in the analog signal, and provides pre-distortion of the digital signal to compensate for non-linearties of the power amplifier.

Abstract: A cellular radio architecture that includes a receiver module having a delta-sigma modulator that converts analog signals to digital signals and a Fast-Fourier transform (FFT) circuit that converts the digital signals to frequency spectrum signals. The architecture also includes a moving average circuit that smoothes out the frequency spectrum signals by applying a moving average to the signals. The architecture further includes a differentiator circuit that differentiates the frequency spectrum signals to make the signals linear, and a minimum finding circuit that converts the differentiated frequency spectrum signals into positive values for frequencies above a notch frequency in the differentiated signals and negative values for frequencies below the notch frequency in the differentiated signals.

Abstract: A cellular radio architecture that includes a transceiver front-end circuit including an antenna and a switch module having a switching network that directs analog transmit signals to be transmitted to the antenna and receives receive signals from the antenna. The architecture further includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer module, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture also includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to the transmit signals. The transmitter module includes a tunable bandpass filter and a power amplifier for amplifying the transmit signals before transmitting. The architecture also includes a calibration feedback and switch module that receives the amplified signals from the power amplifier.

Abstract: A cellular radio architecture that includes a receiver module having a delta-sigma modulator that includes a plurality of gm cells configured in stages, where each stage includes at least two gm cells and an LC filter circuit. The gm cells in each stage can be controlled to be active or inactive to convert, for example, the modulator from a fourth order modulator to a second order modulator to reduce power dissipation. Further, the gm cells can be controlled to optimize a dynamic range of the modulator and to redirect current from inactive cells to active cells in order to optimize power consumption.

Abstract: A cellular radio architecture that includes a receiver module having a delta-sigma modulator that includes a plurality of gm cells configured in stages, where each stage includes at least two gm cells and an LC filter circuit. The gm cells in each stage can be controlled to be active or inactive to convert, for example, the modulator from a fourth order modulator to a second order modulator to reduce power dissipation. Further, the gm cells can be controlled to optimize a dynamic range of the modulator and to redirect current from inactive cells to active cells in order to optimize power consumption.

Abstract: A cellular radio architecture that includes an RF transmitter having a digital signal processor, a digital-to-analog converter (DAC) module that converts digital bits from the processor to an analog signal, a tunable bandpass filter that removes frequencies in the analog signal outside of a frequency band of interest, and a power amplifier that amplifies the filtered analog signal. The architecture also includes a calibration feedback device that receives the amplified analog signal and provides a feedback signal to the processor for calibrating the digital signal to provide amplified amplifier pre-distortion. The processor employs a noise-shaping operation to shape the analog signal from the DAC to remove quantization noise in an immediate vicinity of the signal to improve signal-to-noise ratio, performs an infinite impulse response process to lower a noise floor in the analog signal, and provides pre-distortion of the digital signal to compensate for non-linearties of the power amplifier.

Abstract: A cellular radio architecture that includes a receiver module having a delta-sigma modulator that converts analog signals to digital signals and a Fast-Fourier transform (FFT) circuit that converts the digital signals to frequency spectrum signals. The architecture also includes a moving average circuit that smoothes out the frequency spectrum signals by applying a moving average to the signals. The architecture further includes a differentiator circuit that differentiates the frequency spectrum signals to make the signals linear, and a minimum finding circuit that converts the differentiated frequency spectrum signals into positive values for frequencies above a notch frequency in the differentiated signals and negative values for frequencies below the notch frequency in the differentiated signals.

Abstract: A cellular radio architecture that includes a transceiver front-end circuit including an antenna and a switch module having a switching network that directs analog transmit signals to be transmitted to the antenna and receives receive signals from the antenna. The architecture further includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer module, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture also includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to the transmit signals. The transmitter module includes a tunable bandpass filter and a power amplifier for amplifying the transmit signals before transmitting. The architecture also includes a calibration feedback and switch module that receives the amplified signals from the power amplifier.

Abstract: A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a multiplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer.

Abstract: A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a multiplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer.

Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.

Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.