Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.

Abstract: Techniques pertaining to dynamic enablement, disablement and adjustment of offset of a virtual periodic timing control signal based on one or more predefined events are described. A method may determine whether a first predefined event is beginning. The method may also enable an offset of the virtual periodic timing control signal for synchronizing one or more first system modules in response to a determination that the first predefined event is beginning. The one or more first system modules may be configured to control one or more operations of one or more second system modules. The one or more second system modules may be configured to process one or more image frames. The method may further determine whether the first predefined event is ending. The method may additionally disable the offset in response to a determination that the first predefined event is ending.

Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.

Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.

Abstract: Techniques pertaining to dynamic enablement, disablement and adjustment of offset of a virtual periodic timing control signal based on one or more predefined events are described. A method may determine whether a first predefined event is beginning. The method may also enable an offset of the virtual periodic timing control signal for synchronizing one or more first system modules in response to a determination that the first predefined event is beginning. The one or more first system modules may be configured to control one or more operations of one or more second system modules. The one or more second system modules may be configured to process one or more image frames. The method may further determine whether the first predefined event is ending. The method may additionally disable the offset in response to a determination that the first predefined event is ending.

Abstract: A memory management method includes: performing a first-level collection operation upon first storage units in a memory pool allocated in a memory device; and after the first storage units are processed by the first-level collection operation, performing a second-level collection operation upon second storage units in the memory pool allocated in the memory device, wherein one of the first-level collection operation and the second-level collection operation is a page-level collection operation, and another of the first-level collection operation and the second-level collection operation is a bank-level collection operation.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: A multi-display system and method for displaying tearing free video frames thereon is disclosed. The present invention eliminates the conventional tearing defect by starting the pixel data updating of a display pattern after a last pixel of the display pattern has been displayed on a display device of the multi-display system having a lower refresh frequency, and pausing the pixel data updating of a specific pixel, which is not displayed on another display device of the multi-display system having a higher refresh frequency, until the specific pixel has been displayed.

Abstract: A method for nested flow control is disclosed. The method includes providing a predicate register and a branch register; receiving a plurality of instructions including flow control instructions; storing a depth level with the branch register each time a flow control instruction is fetched or decoded or executed; setting the predicate register according to an evaluation result of the flow control instruction; and executing instructions following the flow control instruction according to the predicate register and the branch register.

Abstract: A method for processing predetermined instructions in a processing system having a plurality of processing units includes providing a global program counter and setting a counter value of the global program counter as an instruction of the predetermined instructions is executed; assigning each processing unit a local program counter and setting a counter value of the local program counter according to a current instruction being executed by the processing unit; and enabling at least one of the processing units to execute a specific instruction of the predetermined instructions according to counter values stored in local program counters of the processing units and the global program counter.