Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Abstract: An electrically erasable programmable read only memory (EEPROM) includes a substrate, bit lines, a row of erase gate and a row of floating gates. The bit lines are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the bit lines. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter.

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.