Abstract: Systems and methods are described for network address lookup entry aging in a DRAM memory. A method of DRAM data aging includes: refreshing a row of memory cells in an array of DRAM memory cells. The refreshing periodically includes aging all entries that are stored in the row of memory cells. The systems and methods provide advantages in that an existing operation is used for an additional function. In addition, the aging can be implemented with closely coupled logic using the sense amplifiers.

Abstract: Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.

Abstract: A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place.

Abstract: Systems and methods are described for combining a plurality of memory sections with a controller, all in a single semiconductor chip. A data processing chip has two or more DRAM memory sections with at least one section being divided into a number of arrays. Data is stored in a particular memory section depending on its associated task. For instance, pixel data is stored in a frame buffer memory section, whereas data relating to pattern, cursor, and video line buffers are stored in an auxiliary memory section. These two separate sections of memory have their own set of address, read/write, activate, control and data lines. Hence, they can be accessed independently by the memory controller. Furthermore, a memory section can be subdivided into a number of distinct arrays. For the subdivided memory section, two separate and distinct address/control buses are implemented to access these arrays. The first address bus is used to specify which selected row within one of these arrays is to be activated.

Abstract: A method and apparatus for configuring memory within a dual access dynamic random access memory (DRAM) frame buffer so that array conflicts are reduced between neighboring pixels. The present invention DRAM frame buffer contains a number of arrays (e.g., 48), each array containing a number of rows (e.g., 256), each row contains a number of bytes (e.g., 1024). Rows of arrays are used to store frame buffer information within the DRAM. There is a single row of sense amplifiers per array, so rows of the same array conflict since they cannot be open at the same time. In an alternative embodiment, some neighboring arrays share the same row of sense amplifiers so neighboring arrays can conflict. The DRAM memory is configured such that for any given central pixel, its four spatially neighboring pixels (up, down, right and left) are not stored (1) in a different row of the same array as the central pixel nor (2) stored in a different row of any other conflicting array.