Patents by Inventor Hsueh-Hsing Liu

Hsueh-Hsing Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11233173
    Abstract: An ultraviolet C light-emitting diode including an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a two-dimensional hole gas (2DHG) inducing layer, and an electron blocking layer is provided. The active layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength of a maximum peak of a spectrum emitted by the active layer ranges from 230 nm to 280 nm. The two-dimensional hole gas (2DHG) inducing layer is disposed between the active layer and the p-type semiconductor layer. A concentration of magnesium in the 2DHG inducing layer is less than 1017 atoms/cm3. The electron blocking layer is disposed between the p-type semiconductor layer and the 2DHG inducing layer. A concentration of magnesium in a part of the electron blocking layer adjacent to the 2DHG inducing layer is greater than 1019 atoms/cm3.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 25, 2022
    Assignees: Industrial Technology Research Institute, OPTO TECH CORP.
    Inventors: Chia-Lung Tsai, Hsueh-Hsing Liu, Chang Da Tsai
  • Patent number: 10957814
    Abstract: An ultraviolet C light-emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a first electron blocking layer, and a second electron blocking layer. The active layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer. The wavelength of the maximum peak of the spectrum emitted by the active layer ranges from 230 nanometers to 280 nanometers. The concentration of magnesium in the active layer is less than 1017 atoms/cm3. The first electron blocking layer and the second electron blocking layer are disposed between the p-type semiconductor layer and the active layer. The concentration of magnesium in the second electron blocking layer is greater than that of the first electron blocking layer and is greater than 1018 atoms/cm3.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 23, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Lung Tsai, Hsueh-Hsing Liu
  • Publication number: 20210005780
    Abstract: An ultraviolet C light-emitting diode including an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a two-dimensional hole gas (2DHG) inducing layer, and an electron blocking layer is provided. The active layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength of a maximum peak of a spectrum emitted by the active layer ranges from 230 nm to 280 nm. The two-dimensional hole gas (2DHG) inducing layer is disposed between the active layer and the p-type semiconductor layer. A concentration of magnesium in the 2DHG inducing layer is less than 1017 atoms/cm3. The electron blocking layer is disposed between the p-type semiconductor layer and the 2DHG inducing layer. A concentration of magnesium in a part of the electron blocking layer adjacent to the 2DHG inducing layer is greater than 1019 atoms/cm3.
    Type: Application
    Filed: August 31, 2020
    Publication date: January 7, 2021
    Applicants: Industrial Technology Research Institute, OPTO TECH CORP.
    Inventors: Chia-Lung Tsai, Hsueh-Hsing Liu, Chang Da Tsai
  • Publication number: 20200194618
    Abstract: An ultraviolet C light-emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a first electron blocking layer, and a second electron blocking layer. The active layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer. The wavelength of the maximum peak of the spectrum emitted by the active layer ranges from 230 nanometers to 280 nanometers. The concentration of magnesium in the active layer is less than 1017 atoms/cm3. The first electron blocking layer and the second electron blocking layer are disposed between the p-type semiconductor layer and the active layer. The concentration of magnesium in the second electron blocking layer is greater than that of the first electron blocking layer and is greater than 1018 atoms/cm3.
    Type: Application
    Filed: June 5, 2019
    Publication date: June 18, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Lung Tsai, Hsueh-Hsing Liu
  • Patent number: 10074533
    Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 ?m and a height between 1 and 500 ?m.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 11, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Chun Yeh, Kan-Hsueh Tsai, Chuan-Wei Tsou, Heng-Yuan Lee, Hsueh-Hsing Liu, Han-Chieh Ho, Yi-Keng Fu
  • Patent number: 9970880
    Abstract: An apparatus for measuring a curvature of a thin film includes a light emitting module, a first optical module, a second optical module, a third optical module, and an image analysis module. The light emitting module emits a single laser to be used as an incident light. The incident light is transmitted through a first optical path provided by the first optical module, then the incident light is guided by the second optical module to be incident to the thin film through a second optical path. A reflected light reflected by the thin film is transmitted through the second optical path, then guided by the third optical module to be transmitted along a third optical path. The image analysis module determines the curvature of the thin film according to the characteristic of the reflected light.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Tzung-Te Chen, Hsueh-Hsing Liu, Chun-Wen Chu, Yi-Keng Fu
  • Publication number: 20180052115
    Abstract: An apparatus for measuring a curvature of a thin film includes a light emitting module, a first optical module, a second optical module, a third optical module, and an image analysis module. The light emitting module emits a single laser to be used as an incident light. The incident light is transmitted through a first optical path provided by the first optical module, then the incident light is guided by the second optical module to be incident to the thin film through a second optical path. A reflected light reflected by the thin film is transmitted through the second optical path, then guided by the third optical module to be transmitted along a third optical path. The image analysis module determines the curvature of the thin film according to the characteristic of the reflected light.
    Type: Application
    Filed: December 19, 2016
    Publication date: February 22, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Tzung-Te Chen, Hsueh-Hsing Liu, Chun-Wen Chu, Yi-Keng Fu
  • Patent number: 8679881
    Abstract: A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 25, 2014
    Assignee: Tekcore Co., Ltd.
    Inventors: Jen-Inn Chyi, Lung-Chieh Cheng, Hsueh-Hsing Liu, Geng-Yen Lee
  • Patent number: 8586995
    Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: November 19, 2013
    Assignee: National Central University
    Inventors: Jen-Inn Chyi, Geng-Yen Lee, Hsueh-Hsing Liu
  • Publication number: 20130240895
    Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
    Type: Application
    Filed: August 9, 2012
    Publication date: September 19, 2013
    Inventors: Jen-Inn CHYI, Geng-Yen Lee, Hsueh-Hsing Liu
  • Patent number: 8524583
    Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate, each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 3, 2013
    Assignee: National Central University
    Inventors: Jen-Inn Chyi, Hsueh-Hsing Liu, Hsien Yu Lin
  • Publication number: 20120276722
    Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate , each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.
    Type: Application
    Filed: July 6, 2011
    Publication date: November 1, 2012
    Inventors: Jen-Inn CHYI, Hsueh-Hsing Liu, Hsien Yu Lin
  • Patent number: 8237174
    Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: August 7, 2012
    Assignee: National Central University
    Inventors: Peng-Ren Chen, Hsueh-Hsing Liu, Jen-Inn Chyi
  • Publication number: 20110272719
    Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Inventors: Peng-Ren Chen, Hsueh-Hsing Liu, Jen-Inn Chyi
  • Patent number: 8048786
    Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: November 1, 2011
    Assignee: National Central University
    Inventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu
  • Publication number: 20110045658
    Abstract: A method for fabricating a semi-polar nitride semiconductor is disclosed, comprising following steps: firstly, a (001) substrate tilted at 7 degrees and having a plurality of V-like grooves is provided, and tilted surfaces of the V-like groove are a (111) surface at 61.7 degrees and a ( 1 11) surface at 47.7 degrees; next, a surface of said substrate is cleaned by using a deoxidized solution, and then a buffer layer is formed on said substrate to cover said V-like grooves; then, said buffer layer is covered with an oxide layer except for said buffer layer formed on said (111) surface at 61.7 degrees; and finally, said semi-polar nitride semiconductor is formed on said buffer layer having (111) surface at 61.7 degrees to enhance the quality of said semi-polar nitride semiconductor.
    Type: Application
    Filed: December 17, 2009
    Publication date: February 24, 2011
    Inventors: Hsueh-hsing LIU, Jen-inn Chyi, Chin-chi Wu
  • Publication number: 20100068872
    Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.
    Type: Application
    Filed: November 3, 2008
    Publication date: March 18, 2010
    Inventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu