Patents by Inventor Hsueh-I Huang
Hsueh-I Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9302904Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: GrantFiled: September 25, 2014Date of Patent: April 5, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Publication number: 20150044808Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: ApplicationFiled: September 25, 2014Publication date: February 12, 2015Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 8897470Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: GrantFiled: July 31, 2009Date of Patent: November 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 8362558Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: May 4, 2011Date of Patent: January 29, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 8354716Abstract: A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.Type: GrantFiled: July 2, 2010Date of Patent: January 15, 2013Assignee: Macronix International Co., Ltd.Inventors: Hsueh I Huang, Ming-Tung Lee, Shyi-Yuan Wu
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Patent number: 8125031Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: May 4, 2011Date of Patent: February 28, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20120037989Abstract: LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Shuo-Lun Tu, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan WU
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Publication number: 20120001260Abstract: A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Inventors: Hsueh I. Huang, Ming-Tung Lee, Shyi-Yuan Wu
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Patent number: 8017486Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: June 22, 2007Date of Patent: September 13, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20110204441Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20110026742Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.Type: ApplicationFiled: July 31, 2009Publication date: February 3, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
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Publication number: 20080315308Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu