Patents by Inventor Hsueh-Jen Yang

Hsueh-Jen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20230378268
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Tai CHAN, Yu-Ching HUANG, Chien-Chih LIN, Hsueh-Jen YANG
  • Patent number: 9178063
    Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 3, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Publication number: 20140346614
    Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Wei-Yuan LU, Li-Ping HUANG, Han-Ting TSAI, Wei-Ching WANG, Ming-Shuan LI, Hsueh-Jen YANG, Kuan-Chung CHEN
  • Patent number: 8828817
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8754477
    Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8735963
    Abstract: A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Hsueh-Jen Yang
  • Publication number: 20130187221
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Publication number: 20130099314
    Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Publication number: 20100001335
    Abstract: A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Hsueh-Jen Yang