Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

Abstract: In one implementation, a diode providing a substantially oscillation free fast-recovery includes at least one anode diffusion formed at a front side of a semiconductor die, and a cathode layer formed at a back side of the semiconductor die. The diode also includes a drift region and a buffer layer situated between the drift region and the cathode layer to enable the substantially oscillation free fast-recovery by the diode. In one implementation, the buffer layer is N type doped using hydrogen as a dopant.

Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

Abstract: A U-shape Metal-Oxide-Semiconductor (UMOS) device comprises a P-base layer, an N+ source region disposed in the P-base layer where the source region has a first surface coplanar with a first surface of the P-base layer, a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and floor enclosing a trench interior region, a conducting gate material filling the trench interior region, a first accumulation channel layer disposed along a first side wall of the U-shape trench and in contact with the source region and a first side wall of the U-shape trench, a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer, and an N-drift region where the P-junction gate is disposed between the dielectric layer and the N-drift region.

Abstract: A U-shape Metal-Oxide-Semiconductor (UMOS) device comprises a P-base layer, an N+ source region disposed in the P-base layer where the source region has a first surface coplanar with a first surface of the P-base layer, a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and floor enclosing a trench interior region, a conducting gate material filling the trench interior region, a first accumulation channel layer disposed along a first side wall of the U-shape trench and in contact with the source region and a first side wall of the U-shape trench, a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer, and an N-drift region where the P-junction gate is disposed between the dielectric layer and the N-drift region.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.

Abstract: A high power FET switch comprises an N? drift layer, in which pairs of trenches are recessed to a predetermined depth; oxide side-walls extend to the trench bottoms, and each trench is filled with a conductive material. N+ and metal layers on opposite sides of the drift layer provide drain and source connections for the FET, and the conductive material in each trench is connected together to provide a gate connection. A shallow P region extends across the bottom and around the corners of each trench's side-walls into the drift layer. The application of a sufficient gate voltage causes holes to be injected from the shallow P regions into the N? drift layer, thereby modulating the drift layer's conductivity and lowering the device's on-resistance, and enabling current to flow between the drain and source connections.

Abstract: A high power FET switch comprises an N? drift layer, in which pairs of trenches are recessed to a predetermined depth; oxide side-walls extend to the trench bottoms, and each trench is filled with a conductive material. N+ and metal layers on opposite sides of the drift layer provide drain and source connections for the FET, and the conductive material in each trench is connected together to provide a gate connection. A shallow P region extends across the bottom and around the corners of each trench's side-walls into the drift layer. The application of a sufficient gate voltage causes holes to be injected from the shallow P regions into the N? drift layer, thereby modulating the drift layer's conductivity and lowering the device's on-resistance, and enabling current to flow between the drain and source connections.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a drift layer, with a p-n junction formed below a gate adjacent to the drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage controlled using an insulated gate.

Abstract: A high power switch includes diode and BJT structures interdigitated in a drift layer and separated by insulated trench gates; electrodes contacting the diode and BJT structures provide anode and cathode connections. Shallow N+ regions extend below and around the corners of the oxide side-walls and bottoms of respective gates. A voltage applied across the anode and cathode sufficient to forward bias the diode's p-n junction causes electrons to be injected which provide a base drive current to the BJT sufficient to turn it on and enable current to flow from anode to cathode via the diode and BJT structures. A gate voltage sufficient to reverse bias the junction between the shallow N+ regions and the drift layer forms a potential barrier which blocks current flow through the diode and BJT structures and eliminates the base drive current such that the BJT and said switch are turned off.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a drift layer, with a p-n junction formed below a gate adjacent to the drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage controlled using an insulated gate.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.

Abstract: An insulated-gate bipolar switch contains a number of trench-IGBT structures interdigitated with a number of floating mesas and trench gates to reduce inversion channel density. The IGBT mesa widths and the floating mesa widths are made different, which enables the switch to provide desired VFD, SCSOA and RBSOA values. The mesa widths and the number of floating mesas per unit cell are adjusted as needed to provide a switch having desired characteristics.

Abstract: A trench insulated-gate bipolar transistor (IGBT) comprises a number of trench-IGBT structures interdigitated with bipolar transistor (BJT) structures in a drift layer, with trench gates separating the structures. Shallow P regions span the bottom corners of respective trench gates to protect the trench oxide from high peak electric fields encountered when the device is reverse-biased. Because no inversion channels form across the BJT mesas in response to a gate voltage, base drive and thus the device's saturation current level is reduced and a robust short-circuit SOA is provided. The ratio of IGBT structures to BJT structures is adjusted as needed to obtain a desired saturation current level and short-circuit SOA.

Abstract: A high power unipolar FET switch has an N− drift layer; a layer of metal contacts the drift layer via an ohmic contact to provide a drain connection for the FET. Each switch cell has a pair of trenches recessed into the drift layer and separated by a mesa region. Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material; the conductive material in each trench is connected together to provide a gate connection for the FET. A shallow P region extends from the bottom of each trench into the drift layer and around the trench corners. A layer of metal contacts the mesa region via an ohmic contact to provide a source connection for the FET. The structure preferably operates as a “normally-off” device, with the potentials created by the work function difference between the conductive material and the N− mesa region completely depleting the mesa region.

Abstract: A high power rectifier device has an N− drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls, a shallow P+ region at the bottom of the trench, and a conductive material between the top of the trench and its shallow P+ region. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts. Forward conduction through both Schottky and P+ regions occurs when the device is forward-biased, with the Schottky contact's low barrier height providing a low forward voltage drop. When reversed-biased, depletion regions around the shallow P+ regions and the side-walls provide a potential barrier which shields the Schottky contacts, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: A high power rectifier device has an − drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls and an oxide bottom, and is filled with a conductive material. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts at the metal-mesa interface. Shallow P regions extend from the bottom of each trench into the drift layer. Forward conduction occurs when the Schottky contact's barrier height is overcome. When reversed-biased, depletion regions form around the shallow P regions and the oxide side-walls which provide potential barriers across the mesa regions that shield the Schottky contacts from high electric fields, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: Sodium loss, free halide build-up, devitrification and wall etching of the arc chamber are substantially reduced in an electrodeless HID metal halide arc discharge lamp by a protective metal silicate coating present only on the interior, equatorial portion of the arc chamber wall which is closest to the arc plasma. Suitable coatings include a metal silicate of a metal selected from the group consisting essentially of scandium, yttrium, beryllium, rare earth metal and mixture thereof.

Abstract: Silver metal and nickel silicide are added to the fill of an electrodeless high intensity metal halide discharge lamp, which includes at least one metal iodide as a fill ingredient, for controlling the iodine vapor level therein. The nickel silicide acts to getter oxygen which has been introduced into the arc tube during lamp processing, thereby avoiding oxidation of the metal iodide portion of the fill and a concomitant release of free iodine into the arc tube. The silver acts to getter free iodine available from the metal iodide(s) of the fill as metal diffuses into the quartz arc tube wall, forming silver iodide (AgI). The combination of silver and nickel silicide acts to control the iodine level below an arc instability threshold to promote and maintain arc stability. In addition, neither silver nor nickel silicide attack the quartz arc tube wall. Lamp performance and lamp life are thus substantially improved.