Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

Abstract: An embodiment of a method for generating a population of amplified concatamer products is described that comprises amplifying a template nucleic acid molecule using a first nucleic acid primer immobilized on a bead substrate and a second nucleic acid primer in solution to generate a population of substantially identical copies of the template nucleic acid molecule immobilized on the bead substrate; and amplifying the population of substantially identical copies of the template nucleic acid molecule using a concatamer primer that comprises a first region complementary to an end region of the population of substantially identical copies of the template nucleic acid molecule and a second region to generate a population of immobilized concatamer products of the substantially identical copies of the template nucleic acid molecule.

Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

Abstract: An embodiment of a method for generating a population of amplified concatamer products is described that comprises amplifying a template nucleic acid molecule using a first nucleic acid primer immobilized on a bead substrate and a second nucleic acid primer in solution to generate a population of substantially identical copies of the template nucleic acid molecule immobilized on the bead substrate; and amplifying the population of substantially identical copies of the template nucleic acid molecule using a concatamer primer that comprises a first region complementary to an end region of the population of substantially identical copies of the template nucleic acid molecule and a second region to generate a population of immobilized concatamer products of the substantially identical copies of the template nucleic acid molecule.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a bipolar junction transistor (BJT) is formed on the substrate, a metal-oxide semiconductor (MOS) transistor is formed on the substrate and electrically connected to the BJT, a resistor is formed on the substrate and electrically connected to the MOS transistor, a dielectric layer is formed on the substrate to cover the BJT, the MOS transistor, and the resistor, and an oxide-semiconductor field-effect transistor (OS-FET) is formed on the dielectric layer and electrically connected to the MOS transistor and the resistor.

Abstract: An embodiment of a method for generating a population of amplified concatamer products is described that comprises amplifying a template nucleic acid molecule using a first nucleic acid primer immobilized on a bead substrate and a second nucleic acid primer in solution to generate a population of substantially identical copies of the template nucleic acid molecule immobilized on the bead substrate; and amplifying the population of substantially identical copies of the template nucleic acid molecule using a concatamer primer that comprises a first region complementary to an end region of the population of substantially identical copies of the template nucleic acid molecule and a second region to generate a population of immobilized concatamer products of the substantially identical copies of the template nucleic acid molecule.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: The invention describes a method for lowering particle count after tungsten etch back, in which method a plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.

Abstract: The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality of first dopants are implanted on a surface of the electrode to form a first doped region. Then a plurality of second dopants are implanted into the electrode to form a second doped region below the first doped region. Then the capacitor is formed comprising the electrode. The first doped region and the second region can reduce voltage coefficient as well as increase capacitance of the capacitor.

Abstract: This invention increases the overlapped area between the diffusion area and the borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in a photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases the overlapped area between the borderless contact and the active area, and reduces borderless contact leakage.

Abstract: This invention increases overlapped area between diffusion area and borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases overlapped area between the borderless contact and said active area, and reduces borderless contact leakage.

Abstract: The invention describes a method for lowering particle count after tungsten etch back, in which method a plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.