Abstract: A method for dynamically adjusting a header region RF gain of a variable gain amplifier while accessing header regions of a DVD-RAM disc, and apparatus thereof. The method includes the following steps: irradiating a light spot on the DVD-RAM disc with a pickup head; detecting a 4T peak-to-peak level of a RF signal generated by the variable gain amplifier while the light spot is moving within a VFO1 column of a header region of the DVD-RAM disc; comparing the 4T peak-to-peak level with a target level; adjusting a header region RF gain of the variable gain amplifier according to a result of the comparing step.

Abstract: A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a low-pass filter for receiving the wobble signal and filtering the wobble signal to generate a filtered signal, a comparator for comparing the wobble signal with the filtered signal and generating a compared signal, and a detecting unit for receiving the compared signal and generating a bit signal according to the duty cycle of the compared signal. The bit signal is a first value when the duty cycle of the compared signal is greater than a predetermined value, and the bit signal is a second value when the duty cycle of the compared signal is smaller than the predetermined value.

Abstract: A method for dynamically adjusting a header region RF gain of a variable gain amplifier while accessing header regions of a DVD-RAM disc, and apparatus thereof. The method includes the following steps: irradiating a light spot on the DVD-RAM disc with a pickup head; detecting a 4T peak-to-peak level of a RF signal generated by the variable gain amplifier while the light spot is moving within a VFO1 column of a header region of the DVD-RAM disc; comparing the 4T peak-to-peak level with a target level; adjusting a header region RF gain of the variable gain amplifier according to a result of the comparing step.

Abstract: An automatic gain control device without being influenced by leakage current of a capacitor. The automatic gain control device includes a first control loop, a second control loop, and a multiplexer. The first control loop receives an input voltage and generates a first control voltage. The second control loop receives the first control voltage, digitizes the first control voltage, and outputs a second control voltage by a DAC. The multiplexer chooses the first control voltage or the second control voltage as a gain control voltage according to a hold signal. Because the second control loop digitizes and holds the first control voltage and output the second control voltage from the DAC, the gain control voltage can be held constant for a long time without being influenced by leakage current.

Abstract: A control module for an automatic gain control device of an optical disc playback apparatus includes a constant-gain setting member and a switch member. The playback apparatus includes an optical pickup head for reading an optical disc. The constant-gain setting member provides a constant gain signal. The switch member connects the constant-gain setting member to the automatic gain control device so as to set the automatic gain control device at a predetermined gain when the optical pickup head reads a non-recorded area of the optical disc or performs a track jump operation.

Abstract: An automatic gain control device without being influenced by leakage current of a capacitor. The automatic gain control device includes a first control loop, a second control loop, and a multiplexer. The first control loop receives an input voltage and generates a first control voltage. The second control loop receives the first control voltage, digitizes the first control voltage, and outputs a second control voltage by a DAC. The multiplexer chooses the first control voltage or the second control voltage as a gain control voltage according to a hold signal. Because the second control loop digitizes and holds the first control voltage and output the second control voltage from the DAC, the gain control voltage can be held constant for a long time without being influenced by leakage current.

Abstract: A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a low-pass filter for receiving the wobble signal and filtering the wobble signal to generate a filtered signal, a comparator for comparing the wobble signal with the filtered signal and generating a compared signal, and a detecting unit for receiving the compared signal and generating a bit signal according to the duty cycle of the compared signal. The bit signal is a first value when the duty cycle of the compared signal is greater than a predetermined value, and the bit signal is a second value when the duty cycle of the compared signal is smaller than the predetermined value.

Abstract: A differential charge pump circuit for eliminating influence of mismatches between current sources is disclosed. The differential charge pump circuit includes a floating capacitor for providing an output voltage, a slicer for outputting a comparison signal to control a charge/discharge actions of the floating capacitor, a first current source, a second current source, a first-common-mode current source, a second-common-mode current source, and a third-common-mode current source connected in parallel with the first current source. The differential charge pump circuit of the present invention utilizes switches to switch the charge and discharge current paths of the capacitor with respect to the common mode current source and the charge/discharge current source. Therefore, the duty cycle of the output signal is free from being adversely influenced by the mismatches between the current sources.

Abstract: A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal.

Abstract: An automatic gain control device without being influenced by leakage current of a capacitor. The automatic gain control device includes a first control loop, a second control loop, and a multiplexer. The first control loop receives an input voltage and generates a first AGC voltage accordingly. The second control loop receives the first AGC voltage, registers the first AGC voltage as digital data, and outputs a second AGC voltage by a DAC. The multiplexer chooses the first AGC voltage or the second AGC voltage as an AGC voltage according to a hold signal. Because the second control loop registers the first AGC voltage in a digital format and output the second AGC voltage from the DAC, the AGC voltage can be held constant for a long time without being influenced by leakage current.

Abstract: An automatic gain control device without being influenced by leakage current of a capacitor. The automatic gain control device includes a first control loop, a second control loop, and a multiplexer. The first control loop receives an input voltage and generates a first AGC voltage accordingly. The second control loop receives the first AGC voltage, registers the first AGC voltage as digital data, and outputs a second AGC voltage by a DAC. The multiplexer chooses the first AGC voltage or the second AGC voltage as an AGC voltage according to a hold signal. Because the second control loop registers the first AGC voltage in a digital format and output the second AGC voltage from the DAC, the AGC voltage can be held constant for a long time without being influenced by leakage current.

Abstract: A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal.

Abstract: A differential charge pump circuit for eliminating influence of mismatches between current sources is disclosed. The differential charge pump circuit includes a floating capacitor for providing an output voltage, a slicer for outputting a comparison signal to control a charge/discharge actions of the floating capacitor, a first current source, a second current source, a first-common-mode current source, a second common-mode current source, and a third-common-mode current source connected in parallel with the first current source. The differential charge pump circuit of the present invention utilizes switches to switch the charge and discharge current paths of the capacitor with respect to the common mode current source and the charge/discharge current source. Therefore, the duty cycle of the output signal is free from being adversely influenced by the mismatches between the current sources.

Abstract: A differential charge pump circuit for eliminating influence of mismatches between current sources and keeping an output signal with 50% duty cycle is disclosed. The differential charge pump circuit includes a capacitor providing an output voltage, a slicer for outputting a comparison signal to control a charge/discharge actions of the capacitor, a first current source, a second current source, a first-common-mode current source, a second-common-mode current source, and a third-common-mode current source connected in parallel with the first current source. The differential charge pump circuit of the present invention utilizes switches to switch the charge and discharge current paths of the capacitor with respect to the common mode current source and the charge/discharge current source. Therefore, the duty cycle of the output signal is free from being adversely influenced by the mismatches between the current sources.

Abstract: A high-speed regeneration comparator is disclosed in the present invention. The high-speed comparator is consisted of two capacitors and two inverters. A first terminal of a first capacitor is coupled with a reference voltage through a first switch and with an inputting voltage through a second switch. The inputting terminal of a first inverter is coupled with a second terminal of the first capacitor and the inputting terminal of the first inverter is coupled with the outputting terminal of the first inverter through a third switch for feedback signals from the outputting terminal of the first inverter to the inputting terminal of the first inverter. A first terminal of a second capacitor is coupled with the outputting terminal of the first inverter.

Abstract: A pseudo two-step current-mode analog-to-digital converter is disclosed, which carries out fine comparison in current mode such that the analog-to-digital conversion can be executed correctly even when the input signal is very small, and thus conserves chip area for implementing the series-connecting resistors.

Abstract: A speed-enhancing comparator with cascaded inverters is disclosed.

Abstract: The two-segment ladder circuit disclosed comprises a front-end resistor for reducing a reference voltage to an internal voltage, a resistor network for receiving the internal voltage and generating a plurality of branch currents having magnitude that form a decreasing geometrical series with a ratio of 1/2, and a resistor for terminating the resistor network. The terminating resistor and resistors of the resistor network can be diffused resistors or well resistors, which require less chip area. In addition, the front-end resistor can be a polysilicon resistor, which is capable of withstanding the high reference voltage and has less resistance variation according to the voltage across it. The two-segment ladder circuit can be used as a building block for a digital-to-analog converters.

Abstract: Methods and circuits are disclosed which terminate charging of a battery when the maximum charge is reached. Maximum charge is reached when the battery voltage has peaked, after a long rise, and just starts to drop. This small voltage drop, or delta, is detected by a charger control which compares the real time battery voltage with a previously sampled battery voltage. Upon detecting this small voltage drop, the charger control terminates the charging process. Implementations using an analog delta voltage detection and a digital delta voltage detection are described.

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references.