Abstract: A touchpad module includes a base plate, a touch member and at least one pressure sensing module. The touch member is located over the base plate. The touch member includes a touch plate and a touch sensitive circuit board. The pressure sensing module is arranged between the base plate and the touch member. The pressure sensing module includes a pressure sensor and a miniature supporting plate. The pressure sensor is installed on the miniature supporting plate. The pressure sensor is electrically connected with the touch sensitive circuit board through the miniature supporting plate. While the touch member is pressed in response to an external pressing force, the pressing force exerted on the touch member is sensed by the at least one pressure sensing module, and the pressure sensing module generates a pressure sensing signal.

Abstract: A touch device includes a touch panel, a circuit board, a vibrating unit and a pressure detection module. The touch panel includes two press regions. When different press regions of the touch panel are pressed by the user, the vibration feedback values generated by different press regions are different.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes: a first circuit, including a first semiconductor substrate, a first group of circuit components formed on the first semiconductor substrate, and a first group of metal layers, wherein, the first group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the first group of metal layers; a second circuit, including a second semiconductor substrate, a second group of circuit components formed on the second semiconductor substrate, and a second group of metal layers, wherein, the second group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the second group of metal layers, and the first circuit and the second circuit being face-to-face stacked and bonded.

Abstract: A buffer circuit includes a first transistor, a second transistor, a feed-forward circuit and a resistive bias circuit. The first transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is served as an input terminal of the buffer circuit. The second transistor has a first terminal and a second terminal, wherein the second terminal of the second transistor is coupled to the third terminal of the first transistor and served as an output terminal of the buffer circuit. The feed-forward circuit has a first terminal and a second terminal respectively coupled to the first terminal of the second transistor and the second terminal of the first transistor. The resistive bias circuit has a first terminal and a second terminal respectively coupled to the second terminal of the first transistor and the first terminal of the feed-forward circuit.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and has an output terminal to output an output signal. The output buffer circuit receives the gray level voltage and the output signal, and compares the gray level voltage and the output signal to generate a comparison result. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal to the output terminal of the output buffer circuit according to the comparison result and a pre-charge enable signal.

Abstract: An equalizing method for a driving device includes determining whether a polarity of an output voltage changes from a first time period to a second time period according to an inversion method of a display device coupled to the driving device, for generating a polarity inversion signal; and determining whether to perform an equalization operation on the output voltage in a switching period between the first time period and the second time period according to the polarity inversion signal, current line information and previous line information.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and has an output terminal to output an output signal. The output buffer circuit receives the gray level voltage and the output signal, and compares the gray level voltage and the output signal to generate a comparison result. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal to the output terminal of the output buffer circuit according to the comparison result and a pre-charge enable signal.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and receives the gray level voltage. The output buffer circuit has an output terminal to output a driving output signal. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal according to the gray level voltage and a pre-charge enable signal, and outputs the pre-charge output signal to the output terminal of the output buffer circuit.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus mentioned above includes a digital-to-analog converter circuit and an output buffer circuit. The digital-to-analog converting circuit receives a display data with a digital format for generating a gray-level voltage. The output buffer circuit has an output terminal to output an output signal. The output buffer circuit receives the gray-level voltage, a pre-charge enable signal and the output signal and provides a pre-charge output signal to the output terminal of the output buffering circuit according to the pre-charge enable signal and a comparison result of the gray-level voltage and the output signal.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and receives the gray level voltage. The output buffer circuit has an output terminal to output a driving output signal. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal according to the gray level voltage and a pre-charge enable signal, and outputs the pre-charge output signal to the output terminal of the output buffer circuit.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: A signal calibration method for synchronizing a clock signal and at least one data signal in a transmission system is disclosed. The signal calibration method comprises detecting at least one transmission time difference between the clock signal and the at least one data signal transmitted in the transmission system, calculating a plurality of delay periods of the clock signal and the at least one data signal according to the at least one transmission time difference, and respectively delaying the clock signal and the at least one data signal for the plurality of delay periods to synchronize the clock signal and the at least one data signal.

Abstract: A display driver apparatus and an inversion method thereof are provided. The display driver apparatus includes a gate drive unit, a source drive unit, a multiplexer unit and a common voltage generation unit. The gate drive unit is used to generate a gate signal for turning on/off sub-pixels. The source drive unit is used to generate a source signal required by the display panel. The multiplexer unit is used to regulate the sequence for the source signal to be delivered to the sub-pixels. The common voltage generation unit is used to generate a common voltage and switch the level of the common voltage during the enable period of the gate signal.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus mentioned above includes a digital-to-analog converter circuit and an output buffer circuit. The digital-to-analog converting circuit receives a display data with a digital format for generating a gray-level voltage. The output buffer circuit has an output terminal to output an output signal. The output buffer circuit receives the gray-level voltage, a pre-charge enable signal and the output signal and provides a pre-charge output signal to the output terminal of the output buffering circuit according to the pre-charge enable signal and a comparison result of the gray-level voltage and the output signal.

Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

Abstract: A display driver apparatus and an inversion method thereof are provided. The display driver apparatus includes a gate drive unit, a source drive unit, a multiplexer unit and a common voltage generation unit. The gate drive unit is used to generate a gate signal for turning on/off sub-pixels. The source drive unit is used to generate a source signal required by the display panel. The multiplexer unit is used to regulate the sequence for the source signal to be delivered to the sub-pixels. The common voltage generation unit is used to generate a common voltage and switch the level of the common voltage during the enable period of the gate signal.

Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

Abstract: Disclosed are use methods, integrated circuits, and manufacturing methods for ferroelectric memory. A data value from multiple data values is received, for example by a state machine controlling the ferroelectric memory. The different data values correspond to different particular durations. The data value corresponding to the selected particular duration is stored in a ferroelectric memory cell by applying voltage to the ferroelectric memory cell for the particular duration.