Patents by Inventor Hsun-Chih Liu

Hsun-Chih Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9523572
    Abstract: An apparatus for measuring of a curvature of a thin film, is adapted to measure the curvature of a thin-film. The apparatus includes a light emitting module, a first optical module, a second optical module, a third optical module, an image capture module, and an image analysis module. The light emitting module emits at least one line laser as an incident light whose cross-sectional shape is a geometric picture formed of lines. The incident light is transmitted through a first optical path formed of the first optical module, and is directed to incident the thin film by the second optical module. The reflected light is reflected by the thin film go through the second optical path, and is directed to transmit through the third optical path by the third optical module, and then is captured by the capture module to form a second geometric picture.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: December 20, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tzung-Te Chen, Chien-Ping Wang, Shang-Ping Ying, Yi-Keng Fu, Hsun-Chih Liu
  • Patent number: 9397281
    Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: July 19, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Publication number: 20160169666
    Abstract: An apparatus for measuring of a curvature of a thin film, is adapted to measure the curvature of a thin-film. The apparatus includes a light emitting module, a first optical module, a second optical module, a third optical module, an image capture module, and an image analysis module. The light emitting module emits at least one line laser as an incident light whose cross-sectional shape is a geometric picture formed of lines. The incident light is transmitted through a first optical path formed of the first optical module, and is directed to incident the thin film by the second optical module. The reflected light is reflected by the thin film go through the second optical path, and is directed to transmit through the third optical path by the third optical module, and then is captured by the capture module to form a second geometric picture.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 16, 2016
    Inventors: Tzung-Te CHEN, Chien-Ping WANG, SHANG-PING YING, Yi-Keng FU, Hsun-Chih LIU
  • Patent number: 9178107
    Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Kuo-Feng Lin, Hsun-Chih Liu, Hung-Lieh Hu, Chien-Jen Sun
  • Patent number: 9159788
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n?2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 13, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Hsun-Chih Liu, Rong Xuan
  • Patent number: 9112077
    Abstract: A semiconductor structure including a silicon substrate, a nucleation layer and a plurality of multi-layer sets is provided. The nucleation layer is disposed on the silicon substrate. The multi-layer sets are stacked over the nucleation layer, and each of the multi-layer sets includes a plurality of first sub-layers and a plurality of second sub-layers stacked alternately. A material of the first sub-layers and the second sub-layers includes Al-containing III-V group compound, wherein an average content of aluminum of the multi-layer sets decreases as a minimum distance between each of the multi-layer sets and the silicon substrate increases, and an aluminum content of the first sub-layers is different from an aluminum content of the second sub-layers.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 18, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Hsun-Chih Liu, Yen-Hsiang Fang, Rong Xuan
  • Publication number: 20150187876
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n?2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Hsun-Chih Liu, Rong Xuan
  • Publication number: 20150137332
    Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 21, 2015
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Patent number: 8952411
    Abstract: A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength ? of light emitted by the active layer is 222 nm???405 nm, and a defect density of the active layer is less than or equal to 5×1010/cm2. The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Patent number: 8779468
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 15, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Patent number: 8759865
    Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Kuo-Feng Lin, Hsun-Chih Liu, Ji-Feng Chen, Hung-Lieh Hu, Chien-Jen Sun
  • Publication number: 20140131732
    Abstract: A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength ? of light emitted by the active layer is 222 nm???405 nm, and a defect density of the active layer is less than or equal to 5×1010/cm2. The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 15, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Publication number: 20140124833
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 8, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140097444
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140097442
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140097443
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Rong Xuan, Chen-Zi Liao, Yi-Keng Fu, Chih-Wei Hu, Chien-Pin Lu, Hsun-Chih Liu
  • Patent number: 8482103
    Abstract: A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: July 9, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Hsun-Chih Liu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan, Chu-Li Chao
  • Publication number: 20120146190
    Abstract: A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsun-Chih Liu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan, Chu-Li Chao
  • Patent number: 8173456
    Abstract: A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 8, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Jenq-Dar Tsay, Suh-Fang Lin, Yu-Hsiang Chang, Yih-Der Guo, Sheng-Huei Kuo, Wei-Hung Kuo, Hsun-Chih Liu
  • Publication number: 20120034714
    Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 9, 2012
    Applicant: INDUTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Jun TSAI, Chen-Peng HSU, Kuo-Feng LIN, Hsun-Chih LIU, Hung-Lieh HU, Chien-Jen SUN