Patents by Inventor Hsun-Chung Kuang

Hsun-Chung Kuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151353
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20210129288
    Abstract: A pad conditioner for conditioning a polishing surface of a polishing pad includes a conditioning disk, a disk holder, and a disk arm. The conditioning disk includes a substrate plate and at least two abrasive segments. The conditioning disk includes at least one channel by which debris and spent slurry may be evacuated. The abrasive segments are on a surface of the substrate plate, and form at least one channel segment therebetween. Each channel segment extends from about the center of the surface to substantially the outer rim of the substrate plate. The disk holder to which the conditioning disk is mounted includes a through hole. The disk arm to which the conditioning disk is mounted includes an opening in fluid communication with the at least one channel segment via the through hole for evacuating the debris and spent slurry by a vacuum module.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 6, 2021
    Inventors: Hsien Hua Shen, Hsun-Chung Kuang
  • Patent number: 10991758
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: 10967479
    Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) pad, and an associated method to perform a CMP process. In some embodiments, the CMP pad comprises a polishing layer having a front surface with protruding asperities while a back surface being planar. A film electrode is attached to the back surface of the polishing layer and is isolated from the front surface of the polishing layer. The CMP pad further comprises an insulating layer covering sidewall and bottom surfaces of the film electrode.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Wei Liang, Hsun-Chung Kuang, Yen-Chang Chu
  • Publication number: 20210050220
    Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.
    Type: Application
    Filed: October 14, 2020
    Publication date: February 18, 2021
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Publication number: 20210043443
    Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Tung-He Chou, Sheng-Chau Chen, Ming-Tung Wu, Hsun-Chung Kuang
  • Publication number: 20210013098
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10879077
    Abstract: A planarization apparatus is provided. The planarization apparatus includes a platen, and a grinding wheel. The platen is configured to support a wafer. The grinding wheel is over the platen and configured to grind the wafer. The grinding wheel includes a base ring, and a plurality of grinding teeth mounted on the base ring. The plurality of grinding teeth includes a plurality of grinding abrasives, and the plurality of grinding abrasives is ball type.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Tung Wu, Chun-Kai Lan, Tung-He Chou, Hsun-Chung Kuang
  • Patent number: 10857651
    Abstract: An apparatus for chemical mechanical polishing includes a pad conditioner. The pad conditioner includes a first disk having a first surface and a second disk having a second surface. The first surface has a first plurality of abrasives with a first mean size and the second surface has a second plurality of abrasives with a second mean size greater than the first mean size.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Kai Lan, Tung-He Chou, Ming-Tung Wu, Sheng-Chau Chen, Hsun-Chung Kuang
  • Publication number: 20200335353
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 10790189
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10727077
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 10665449
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200144484
    Abstract: Some embodiments relate to a memory device. The memory device includes a memory cell overlying a substrate, the memory cell includes a data storage structure disposed between a lower electrode and an upper electrode. An upper interconnect wire overlying the upper electrode. A first inter-level dielectric (ILD) layer surrounding the memory cell and the upper interconnect wire. A second ILD layer overlying the first ILD layer and surrounding the upper interconnect wire. A sidewall spacer laterally surrounding the memory cell. The sidewall spacer has a first sidewall abutting the first ILD layer and a second sidewall abutting the second ILD layer.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Publication number: 20200135538
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Publication number: 20200118842
    Abstract: A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: MING-TUNG WU, HSUN-CHUNG KUANG
  • Patent number: 10529913
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell disposed on a substrate, the MRAM cell comprises a magnetic tunnel junction (MTJ) disposed between a lower electrode and an upper electrode. A sidewall spacer arranged along opposite sidewalls of the MRAM cell. An upper interconnect wire directly contacting an upper surface of the upper electrode along an interface continuously extending from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Publication number: 20200006052
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200006638
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell disposed on a substrate, the MRAM cell comprises a magnetic tunnel junction (MTJ) disposed between a lower electrode and an upper electrode. A sidewall spacer arranged along opposite sidewalls of the MRAM cell. An upper interconnect wire directly contacting an upper surface of the upper electrode along an interface continuously extending from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.
    Type: Application
    Filed: August 1, 2018
    Publication date: January 2, 2020
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Patent number: 10510563
    Abstract: A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Tung Wu, Hsun-Chung Kuang