Patents by Inventor Hsun-Chung Kuang

Hsun-Chung Kuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545202
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Publication number: 20220406916
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11527713
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20220392906
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Publication number: 20220393101
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Application
    Filed: July 29, 2021
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220367342
    Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
  • Publication number: 20220367493
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 17, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220359604
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Chun-Kai Lan, Hai-Dang Trinh, Hsun-Chung Kuang
  • Publication number: 20220359823
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20220359609
    Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chia-Hua Lin, Hsun-Chung Kuang, Yu-Hsing Chang, Yao-Wen Chang
  • Patent number: 11495532
    Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
  • Publication number: 20220351766
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 3, 2022
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Publication number: 20220336737
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Publication number: 20220336739
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Publication number: 20220328292
    Abstract: A method of depositing a layer on a semiconductor workpiece is disclosed. The method includes placing the semiconductor workpiece on a wafer chuck in a processing chamber, introducing a first precursor into the processing chamber, introducing a second precursor into the processing chamber, and while the second precursor is in the processing chamber, applying radiation to the semiconductor workpiece, whereby a surface of the semiconductor workpiece is heated. The method also includes, while the second precursor is in the processing chamber, applying a voltage bias to the wafer chuck.
    Type: Application
    Filed: July 29, 2021
    Publication date: October 13, 2022
    Inventors: Hai-Dang Trinh, Hsun-Chung Kuang, Fa-Shen Jiang
  • Publication number: 20220320123
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Bi-Shen Lee, Hsing-Lien Lin, Hsun-Chung Kuang, Yi Yang Wei
  • Publication number: 20220310635
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 29, 2022
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220310449
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20220293429
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 15, 2022
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Publication number: 20220285374
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 8, 2022
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai