Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a first passivation layer disposed on the barrier layer, a plurality of trenches through at least a portion of the first passivation layer, and a conductive plate structure disposed on the first passivation layer. The conductive plate structure includes a base portion over the trenches and a plurality of protruding portions extending from a lower surface of the base portion and into the trenches.

Abstract: A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate, forming a gate structure on the epitaxial stack, forming an insulating layer covering the epitaxial stack and the gate structure, forming a passivation layer on the insulating layer, forming an opening on the gate structure and through the passivation layer to expose the insulating layer, and removing a portion of the insulating layer through the opening to form an air gap between the gate structure and the passivation layer.

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a first passivation layer disposed on the barrier layer, a plurality of trenches through at least a portion of the first passivation layer, and a conductive plate structure disposed on the first passivation layer. The conductive plate structure includes a base portion over the trenches and a plurality of protruding portions extending from a lower surface of the base portion and into the trenches.

Abstract: An allocation method, utilized in a network device comprising an large receive offload (LRO) engine having LRO rings, includes receiving packets which belong to data streams; recording information of the data streams according to the packets; determining priority values corresponding to the data streams according to the information of the data streams; determining a first data stream within the data streams corresponding to a first priority value which is greater than a predefined value; and when there is an available LRO ring within the LRO rings, allocating the available LRO ring to the first data stream; wherein when an LRO ring is allocated to a data stream, a plurality of incoming packets of the data stream are stored in the LRO ring, and the incoming packets stored in the LRO ring are aggregated into large packets by the LRO engine.

Abstract: An allocation method, utilized in a network device comprising an large receive offload (LRO) engine having LRO rings, includes receiving packets which belong to data streams; recording information of the data streams according to the packets; determining priority values corresponding to the data streams according to the information of the data streams; determining a first data stream within the data streams corresponding to a first priority value which is greater than a predefined value; and when there is an available LRO ring within the LRO rings, allocating the available LRO ring to the first data stream; wherein when an LRO ring is allocated to a data stream, a plurality of incoming packets of the data stream are stored in the LRO ring, and the incoming packets stored in the LRO ring are aggregated into large packets by the LRO engine.

Abstract: An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements.

Abstract: An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements.