Patents by Inventor Hsung Jai Im

Hsung Jai Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10193540
    Abstract: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 29, 2019
    Assignee: XILINX, INC.
    Inventors: Jaeduk Han, Hsung Jai Im
  • Patent number: 9841455
    Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 12, 2017
    Assignee: XILINX, INC.
    Inventors: Scott D. McLeod, Hsung Jai Im, Stanley Y. Chen
  • Patent number: 9729170
    Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventors: Arianne B. Roldan, Hsung Jai Im
  • Publication number: 20160341780
    Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Applicant: XILINX, INC.
    Inventors: Scott D. McLeod, Hsung Jai Im, Stanley Y. Chen
  • Patent number: 9294091
    Abstract: An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 22, 2016
    Assignee: XILINX, INC.
    Inventors: Vassili Kireev, Hsung Jai Im
  • Patent number: 8564023
    Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: October 22, 2013
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 8354671
    Abstract: A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: January 15, 2013
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Henley Liu, Jae-Gyung Ahn, Tony Le, Patrick J. Crotty
  • Patent number: 7923811
    Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 12, 2011
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 7834659
    Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 7724600
    Abstract: An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: May 25, 2010
    Assignee: XILINX, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 7710813
    Abstract: An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: May 4, 2010
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Raymond C. Pang, Boon Yong Ang, Serhii Tumakha
  • Patent number: 7688639
    Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: March 30, 2010
    Assignee: Xilinx, Inc.
    Inventors: Sunhom Paak, Boon Yong Ang, Hsung Jai Im, Daniel Gitlin
  • Patent number: 7598749
    Abstract: An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 6, 2009
    Assignee: XILINX, Inc.
    Inventors: Boon Yong Ang, Sunhom Paak, Hsung Jai Im, Kwansuhk Oh, Raymond C. Pang
  • Publication number: 20090224323
    Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: XILINX, INC.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 7567449
    Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: July 28, 2009
    Assignee: XILINX, Inc.
    Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang
  • Patent number: 7501879
    Abstract: An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: March 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Kwansuhk Oh, Raymond C. Pang, Hsung Jai Im, Sunhom Paak
  • Publication number: 20080101146
    Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Applicant: Xilinx, Inc.
    Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang
  • Patent number: 7312625
    Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: December 25, 2007
    Assignee: Xilinx, Inc.
    Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang, Jan L. de Jong
  • Patent number: 7294888
    Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: November 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Sunhom Paak, Boon Yong Ang, Hsung Jai Im, Daniel Gitlin