Patents by Inventor Hua-Chao TSENG

Hua-Chao TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Contact structure for reducing gate resistance and method of making the same
    Patent number: 8765600
    Abstract: A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Long Chang, Chih-Ping Chao, Chun-Hung Chen, Hua-Chao Tseng, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • CONTACT STRUCTURE FOR REDUCING GATE RESISTANCE AND METHOD OF MAKING THE SAME
    Publication number: 20120104471
    Abstract: A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.
    Type: Application
    Filed: October 28, 2010
    Publication date: May 3, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Long CHANG, Chih-Ping CHAO, Chun-Hung CHEN, Hua-Chao TSENG, Jye-Yen CHENG, Harry-Hak-Lay CHUANG