Patents by Inventor Hua-Chun Chiue

Hua-Chun Chiue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8466019
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: June 18, 2013
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
  • Publication number: 20120025308
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
  • Patent number: 8058121
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 15, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
  • Publication number: 20090321825
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 31, 2009
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chu-Feng CHEN, Chung-Ren LAO, Pai-Chun KUO, Chien-Hsien SONG, Hua-Chun CHIUE, An-Hung LIN