Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

Abstract: An overcurrent detection device of the present disclosure has two charge storage circuits, a control module and a counter circuit. The control module controls and provides charge paths of the two charge storage circuits, so that the two charge storage circuits are charged by a reference current and a sensed current respectively, wherein the sensed current is generated by an output current of a low-dropout regulator. The counter circuit obtains a voltage of the charge storage circuit charged by the sensed current, and counts accordingly. When the counting of the counter circuit reaches a specific value, the counter circuit outputs an overcurrent detection signal. When the output current is an overcurrent, the counter circuit first counts to the specific value before the charge storage circuit which is charged by the reference current is charged to a specific voltage.

Abstract: The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: A dynamic biasing control system applicable to a LDO is provided. The LDO includes an error amplifier, and an output terminal of the LDO outputs a first output voltage, and an output terminal of the error amplifier outputs a second output voltage. The dynamic biasing control system includes a differential amplifier for receiving the first output voltage, and generating a control voltage according to the first output voltage; a first adjustable current source for receiving the second output voltage and dynamically outputting a first current, according to the second output voltage, to drive the differential amplifier; a second adjustable current source for receiving the control voltage and dynamically outputting a second current according to the control voltage, to drive the error amplifier.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) is provided in the invention. The SAR ADC includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

Abstract: A voltage holding circuit and an electronic device using thereof are provided. The voltage holding circuit includes a first transistor, a second transistor, and a first capacitor. A first terminal of the first transistor is coupled to an input voltage, and a control terminal of the first transistor receives a control signal. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is an output terminal of the voltage holding circuit, and a control terminal of the second transistor receives the control signal. A first terminal of the first capacitor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. A holding voltage on the first terminal of the first capacitor is maintained by the first capacitor and parasitic diodes of the first transistor and the second transistor.

Abstract: A voltage holding circuit and an electronic device using thereof are provided. The voltage holding circuit includes a first transistor, a second transistor, and a first capacitor. A first terminal of the first transistor is coupled to an input voltage, and a control terminal of the first transistor receives a control signal. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is an output terminal of the voltage holding circuit, and a control terminal of the second transistor receives the control signal. A first terminal of the first capacitor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. A holding voltage on the first terminal of the first capacitor is maintained by the first capacitor and parasitic diodes of the first transistor and the second transistor.