Abstract: A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

Abstract: A barbecue grill has a stand, a grill body, a smoker, and a side board. The smoker is mounted on a side of the stand, communicates with the grill body, and has a smoker body, a smoker cap, an inner box, a smoker grid, and an ash plate. The smoker body has multiple ventilation holes defined through two opposite sides of the smoker body. The smoker cap is pivotally connected to the smoker body to close a top opening of the smoker body. The inner box is mounted in the smoker body and has multiple through holes defined in the inner box and a netted bottom. The smoker grid is mounted on a top of the inner box. The ash plate is slidably mounted on a bottom of the inner box and has multiple ventilation holes selectively aligned with the ventilation holes in the smoker body.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a first electrode over a substrate. A first capacitor dielectric layer is over an upper surface of the first electrode. The upper surface of the first electrode laterally extends to opposing outermost sidewalls of the first capacitor dielectric layer. A second electrode is over the first capacitor dielectric layer. The upper surface of the first electrode extends past opposing sides of the second electrode. A second capacitor dielectric layer is over the second electrode. A third electrode has a lower surface directly over an upper surface of the second capacitor dielectric layer and completely confined over the second electrode.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a lower electrode over a substrate, a first capacitor dielectric layer over the lower electrode, an intermediate electrode over the first capacitor dielectric layer, and a second capacitor dielectric layer is over the intermediate electrode. An upper electrode is over the second capacitor dielectric layer. The upper electrode is completely confined over the intermediate electrode. A first protection layer is completely confined over the intermediate electrode. The first protection layer covers opposing sidewalls of the upper electrode and upper surfaces of the intermediate electrode and the upper electrode.

Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: A semiconductor device assembly is provided. The assembly includes a support layer with an inside surface, a semiconductor device, and an encapsulant material. The encapsulant material includes a bulk material and thermally conductive nanoparticles, each nanoparticle having an electrically insulative shell and an electrically conductive core. The semiconductor device is disposed on the inside surface of the support layer, the thermally conductive nanoparticles are evenly distributed throughout the bulk material, and the encapsulant material at least partially encapsulates the semiconductor device.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

Abstract: An electronic package is provided, in which an electronic structure is embedded in an encapsulation layer, a protective layer is formed on the encapsulation layer, an insulating layer is formed on the protective layer, and at least one blind via is formed penetrating through the insulating layer and the protective layer, so that the electronic structure is exposed from the blind via to make a circuit layer formed on the insulating layer extending into the blind via to electrically connect the electronic structure. Therefore, by the double layer design of the insulating layer and the protective layer, voids generated by the process are free from being transferred to the insulating layer to avoid the voids remaining in the circuit layer.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A system and method for managing a respiratory condition of a user is disclosed. The system includes an oxygen concentrator having a compression system configured to generate oxygen enriched air for delivery to the user. A physiological sensor is configured to collect physiological data of the user. The physiological data is of one or more data types. An operational sensor is configured to collect operational data of the oxygen concentrator during operation of the oxygen concentrator. The operational data is of one or more data types. A processor is configured to receive the collected physiological data and the operational data and compute a summary parameter for values of each data type. The processor is also configured to compute a health score from the summary parameter values.

Abstract: Systems and methods for thermal treatment of a workpiece are provided. In one example, a method for conducting a treatment process on a workpiece, such as a thermal treatment process, an annealing treatment process, an oxidizing treatment process, or a reducing treatment process in a processing apparatus is provided. The processing apparatus includes a plasma chamber and a processing chamber. The plasma chamber and the processing chamber are separated by a plurality of separation grids or grid plates. The separation grids or grid plates operable to filter ions generated in the plasma chamber. The processing chamber has a workpiece support operable to support a workpiece.