Abstract: A fault protection battery cover assembly consists of a platform having a plurality of holes disposed thereon, a positive and a negative terminal for providing electricity output, and a positive and a negative terminal connecting bar for providing connection with an internal circuit. Said terminals and terminal connecting bars are insulatedly disposed at a top and a bottom of said platform. The terminal connecting bars are connected electrically with said terminals by a plurality of fastening elements, and characterized in that a fuse is attached onto said positive terminal to cut off the circuit as overcurrent is generated.

Abstract: An improved structure for gas diffusion electrodes and gas diffusion layers whereby fine gradients of porosity and hydrophobicity promote efficient gas transport, water removal and overall enhanced performance of Membrane Electrode Assemblies constructed with these components.

Abstract: A self-aligned LDD TFT and a fabrication method thereof. The method includes providing a semiconductor layer. A first masking layer is provided over a first region of the semiconductor layer, said first masking layer comprising a material that provide a permeable barrier to a dopant. The semiconductor layer is exposed, including the first region covered by the first masking layer, to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking layer.

Abstract: Provided is a cap assembly for use in cylindrical lithium ion batteries. The cap assembly includes an insulating gasket defining a through hole therein, a rupture plate positioned in the through hole, a vent plate soldered on and electrically connected to the rupture plate, a current interrupt device positioned on the rupture plate, and an end cap assembled on the current interrupt device. The current interrupt device can cut off the current path when the battery discharges at a high discharge rate, so as to improve the safety performance of the lithium ion battery.

Abstract: A center backfire inner heat regenerative energy saving high efficiency furnace and tank integration reduction furnace system comprises a furnace section and a heating section. The furnace section includes a reduction tank, a material inlet door, a magnesium crystal collecting machine, and a residue exhaust pipe. The reduction tank includes a tank body, a centre combustion room, and plural fume exhaust pipes. The material inlet door is connected to a material charging room between the center combustion room and the tank body, and the magnesium crystal collecting machine is provided with a crystal cover communicating with the material charging room, and a water recycling condensation equipment outside the crystal cover. The residue exhaust pipe is connected to the material charging room and provided with a residue exhaust door and a water dispersing heat separating cover. The heating section includes a burner connected to the center combustion room.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: A self-aligned LDD TFT and a fabrication method thereof. The method includes providing a semiconductor layer. A first masking layer is provided over a first region of the semiconductor layer, said first masking layer comprising a material that provide a permeable barrier to a dopant. The semiconductor layer is exposed, including the first region covered by the first masking layer, to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking layer.

Abstract: In a method of passivating a semiconductor device with two types of transistors, e.g., NMOS and PMOS transistor, the semiconductor device is placed in a pressurized sealed chamber and at least two different passivating gases are introduced into the chamber. The two passivating gases can be selected to have one gas suitable for passivating PMOS transistors and the other gas suitable for NMOS transistors.

Abstract: A self-aligned LDD TFT and a fabrication method thereof. A substrate is provided, on which a semiconductor layer is formed. A first masking layer is provided over a first region of the portion of the semiconductor layer. The first masking layer includes a material that provides a permeable barrier to a dopant. The semiconductor layer including the first region covered by the first masking layer is exposed to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking region.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: A thin film transistor (TFT) structure includes a substrate, a polysilicon structure including a plurality of channel regions, at least one lightly doped region and at least one heavily doped source/drain region, a plurality of gate structures, and an insulating layer formed between the gate structures and the polysilicon structure. The thickness of a first portion of the insulating layer under and between the gate structures is greater than the thickness of a second portion of the insulating layer adjacent to the first portion. At least one lightly doped region is formed under the first portion of the insulating layer and at least one heavily doped source/drain region is formed under the second portion of the insulating layer via the same doping procedure.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: A method of passivating a semiconductor device with two types of transistors, e.g., NMOS and PMOS transistors, the semiconductor device is placed in a pressurized sealed chamber and at least two different passivating gases are introduced into the chamber. The two passivating gases can be selected to have one gas suitable for passivating PMOS transistors and the other gas suitable for NMOS transistors.

Abstract: A method for making a thin film transistor (TFT) with a lightly doped region. The process of the invention is compatible with the currently common TFT manufacturing processes. A substrate with a photoresist layer thereon is subjected to two-step exposure with different exposure energies to form a full-through pattern and a non-through pattern after development. The same photoresist layer is subjected to two etching steps to form a gate region and an intra-gate region. The gate region and the intra-gate region are respectively doped with different dopant concentrations. Therefore, the number of times forming and exposing the photoresist layer is reduced.

Abstract: A method for making a thin film transistor (TFT) with a lightly doped region. The process of the invention is compatible with the currently common TFT manufacturing processes. A substrate with a photoresist layer thereon is subjected to two-step exposure with different exposure energies to form a full-through pattern and a non-through pattern after development. The same photoresist layer is subjected to two etching steps to form a gate region and an intra-gate region. The gate region and the intra-gate region are respectively doped with different dopant concentrations. Therefore, the number of times forming and exposing the photoresist layer is reduced.

Abstract: An improved structure for gas diffusion electrodes and gas diffusion layers whereby fine gradients of porosity and hydrophobicity promote efficient gas transport, water removal and overall enhanced performance of Membrane Electrode Assemblies constructed with these components.

Abstract: A rhodium sulfide electrocatalyst formed by heating an aqueous solution of rhodium salt until a steady state distribution of isomers is obtained and then sparging hydrogen sulfide into the solution to form the rhodium sulfide and a membrane electrode assembly with the said electrode and a process for electrolyzing hydrochloric acid.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: A self-aligned LDD TFT and a fabrication method thereof. A substrate is provided, on which a semiconductor layer is formed. A first masking layer is provided over a first region of the portion of the semiconductor layer. The first masking layer comprises a material that provides a permeable barrier to a dopant. The semiconductor layer including the first region covered by the first masking layer is exposed to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking region.

Abstract: A thin film transistor (TFT) structure includes a substrate, a polysilicon structure including a plurality of channel regions, at least one lightly doped region and at least one heavily doped source/drain region, a plurality of gate structures, and an insulating layer formed between the gate structures and the polysilicon structure. The thickness of a first portion of the insulating layer under and between the gate structures is greater than the thickness of a second portion of the insulating layer adjacent to the first portion. At least one lightly doped region is formed under the first portion of the insulating layer and at least one heavily doped source/drain region is formed under the second portion of the insulating layer via the same doping procedure.