Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.

Abstract: Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well.