Patents by Inventor Hua Hong Tan
Hua Hong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136217Abstract: A manufacturing system includes a substrate disposed on a conveyer system. The conveyer system includes a pair of side supports. The substrate is moved on the conveyer system until the substrate is disposed over a bottom support block. The bottom support block is raised to physically contact the substrate. A transfer arm module is provided. The transfer arm module includes a flat bottom surface and an opening formed in the flat bottom surface. The transfer arm module is disposed with the flat bottom surface physically contacting the substrate opposite the bottom support block. A vacuum is enabled through the opening of the transfer arm module. The substrate is lifted off the bottom support block using the vacuum. The substrate is moved over a printing pallet using the transfer arm module. The vacuum is disabled when the substrate is in a positioning area of the printing pallet.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Applicant: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Chee Kay Chow, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Wing Keung Lam
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Patent number: 11945004Abstract: A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.Type: GrantFiled: November 11, 2021Date of Patent: April 2, 2024Assignee: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Wing Keung Lam, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Tao Hu
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Patent number: 11710681Abstract: An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die.Type: GrantFiled: October 6, 2021Date of Patent: July 25, 2023Assignee: UTAC Headquarters Pte. Ltd.Inventors: Tanawan Chaowasakoo, Hua Hong Tan, Alexander Lucero Laylo, Thanawat Jaengkrajarng
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Patent number: 11676934Abstract: The present disclosure is directed to a high throughput clip bonding tool or system which is flexible and easily adapts to different clip bond pitches or sizes. The clip bonding system may be an integrated system with various modules, including a clip singulation module, a feeder module, a transfer module and a clip attach module within a shared footprint. For example, an incoming clip source may be fed to the clip singulation module for clip singulation before the singulated clips are transferred by the feeder and transfer modules to a clip presentation area for clip alignment before pickup. A pickup tool of the clip attach module is configured to facilitate pickup and attachment of clips onto the semiconductor packages to be clip bonded. For example, the pickup head is programmable to facilitate clip bonding process of different applications which may require clips and packages with different sizes.Type: GrantFiled: October 22, 2020Date of Patent: June 13, 2023Assignee: UTAC Headquarters Pte. Ltd.Inventors: Albert Louis Bove, Hua Hong Tan, Aaron Lyn Foong Tan
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Publication number: 20230058682Abstract: A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.Type: ApplicationFiled: November 11, 2021Publication date: February 23, 2023Applicant: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Wing Keung Lam, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Tao Hu
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Publication number: 20220028762Abstract: An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Inventors: Tanawan CHAOWASAKOO, Hua Hong TAN, Alexander Lucero LAYLO, Thanawat JAENGKRAJARNG
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Patent number: 11177301Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.Type: GrantFiled: November 18, 2019Date of Patent: November 16, 2021Assignee: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Chee Kay Chow, Thian Hwee Tan, Wedanni Linsangan Micla, Enrique Jr Sarile, Mario Arwin Fabian, Dennis Tresnado, Antonino Ii Milanes, Ming Koon Ang, Kian Soo Lim, Mauro Jr. Dionisio, Teddy Joaquin Carreon
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Patent number: 11145575Abstract: An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.Type: GrantFiled: November 7, 2019Date of Patent: October 12, 2021Assignee: UTAC Headquarters Pte. Ltd.Inventors: Tanawan Chaowasakoo, Hua Hong Tan, Alexander Lucero Laylo, Thanawat Jaengkrajarng
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Patent number: 11139233Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.Type: GrantFiled: May 28, 2020Date of Patent: October 5, 2021Assignee: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto
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Publication number: 20210118840Abstract: The present disclosure is directed to a high throughput clip bonding tool or system which is flexible and easily adapts to different clip bond pitches or sizes. The clip bonding system may be an integrated system with various modules, including a clip singulation module, a feeder module, a transfer module and a clip attach module within a shared footprint. For example, an incoming clip source may be fed to the clip singulation module for clip singulation before the singulated clips are transferred by the feeder and transfer modules to a clip presentation area for clip alignment before pickup. A pickup tool of the clip attach module is configured to facilitate pickup and attachment of clips onto the semiconductor packages to be clip bonded. For example, the pickup head is programmable to facilitate clip bonding process of different applications which may require clips and packages with different sizes.Type: ApplicationFiled: October 22, 2020Publication date: April 22, 2021Inventors: Albert Louis Bove, Hua Hong Tan, Aaron Lyn Foong Tan
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Publication number: 20200321273Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.Type: ApplicationFiled: May 28, 2020Publication date: October 8, 2020Inventors: Hua Hong TAN, Wilson Poh Leng ONG, Kriangsak Sae LE, Saravuth SIRINORAKUL, Somsak PHUKRONGHIN, Paweena PHATTO
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Patent number: 10707161Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.Type: GrantFiled: August 7, 2018Date of Patent: July 7, 2020Assignee: UTAC Headquarters Pte. Ltd.Inventors: Hua Hong Tan, Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto
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Publication number: 20200161351Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.Type: ApplicationFiled: November 18, 2019Publication date: May 21, 2020Inventors: Hua Hong TAN, Chee Kay CHOW, Thian Hwee TAN, Wedanni Linsangan MICLA, Enrique Jr SARILE, Mario Arwin FABIAN, Dennis TRESNADO, Antonino II MILANES, Ming Koon ANG, Kian Soo LIM, Mauro Jr. DIONISIO, Teddy Joaquin CARREON
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Publication number: 20200144162Abstract: An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.Type: ApplicationFiled: November 7, 2019Publication date: May 7, 2020Inventors: Tanawan CHAOWASAKOO, Hua Hong TAN, Alexander Lucero LAYLO, Thanawat JAENGKRAJARNG
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Patent number: 10354934Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: April 24, 2018Date of Patent: July 16, 2019Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Publication number: 20190043797Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.Type: ApplicationFiled: August 7, 2018Publication date: February 7, 2019Inventors: Hua Hong TAN, Wilson Poh Leng ONG, Kriangsak Sae LE, Saravuth SIRINORAKUL, Somsak PHUKRONGHIN, Paweena PHATTO
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Publication number: 20180240726Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
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Patent number: 9978658Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: November 27, 2016Date of Patent: May 22, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Publication number: 20170077007Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: November 27, 2016Publication date: March 16, 2017Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
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Patent number: 9508623Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: June 5, 2015Date of Patent: November 29, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla