Patents by Inventor Hua-Li HUNG

Hua-Li HUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303255
    Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hua-Li HUNG, Chih-Lun LU, Hsu-Yu HUANG, Tsung-Fan YIN, Ying-Ting HSIA, Yi-Wei CHIU, Li-Te HSU
  • Patent number: 10692762
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
  • Publication number: 20190244849
    Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 8, 2019
    Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
  • Patent number: 10199252
    Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
  • Publication number: 20190019727
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 17, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hua-Li HUNG, Chih-Lun LU, Hsu-Yu HUANG, Tsung-Fan YIN, Ying-Ting HSIA, Yi-Wei CHIU, Li-Te HSU
  • Publication number: 20190006220
    Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.
    Type: Application
    Filed: October 5, 2017
    Publication date: January 3, 2019
    Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
  • Patent number: 10074563
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element is substantially free of oxygen. The semiconductor device structure also includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the gate stack and the spacer element. The semiconductor device structure further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate. An angle between a sidewall of the conductive contact and a top surface of the spacer element is in a range from about 90 degrees to about 120 degrees, and the conductive contact covers a portion of the spacer element.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
  • Publication number: 20180033693
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element is substantially free of oxygen. The semiconductor device structure also includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the gate stack and the spacer element. The semiconductor device structure further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate. An angle between a sidewall of the conductive contact and a top surface of the spacer element is in a range from about 90 degrees to about 120 degrees, and the conductive contact covers a portion of the spacer element.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Li HUNG, Chih-Lun LU, Hsu-Yu HUANG, Tsung-Fan YIN, Ying-Ting HSIA, Yi-Wei CHIU, Li-Te HSU