Patents by Inventor Hua LING
Hua LING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12254931Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.Type: GrantFiled: June 21, 2022Date of Patent: March 18, 2025Assignee: Sandisk Technologies, Inc.Inventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
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Patent number: 12197783Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.Type: GrantFiled: April 28, 2022Date of Patent: January 14, 2025Assignee: SANDISK TECHNOLOGIES LLCInventors: Hua-Ling Cynthia Hsu, Fanglin Zhang
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Publication number: 20250006277Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. Circuitry is configured to program at least some of the plurality of memory cells in a program loop or that is configured to erase at least some of the plurality of memory cells in an erase loop. During the program loop or the erase loop, the circuitry is configured to perform a verify operation and an analog bitscan operation. In the analog bitscan operation, the circuitry counts the memory cells that pass or that fail the verify operation. The circuitry is also configured to determine an output of the analog bitscan operation, the output being one of at least three options.Type: ApplicationFiled: August 7, 2023Publication date: January 2, 2025Applicant: Western Digital Technologies, Inc.Inventors: Hua-Ling Hsu, Henry Chin, Yen-Lung Li, Yanwei He
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Publication number: 20250006266Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.Type: ApplicationFiled: August 9, 2023Publication date: January 2, 2025Applicant: Western Digital Technologies, Inc.Inventors: Hua-Ling Hsu, Henry Chin, Yanwei He
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Publication number: 20250006279Abstract: The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.Type: ApplicationFiled: August 15, 2023Publication date: January 2, 2025Applicant: Western Digital Technologies, Inc.Inventors: Hua-Ling Hsu, Henry Chin, Yanwei He
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Publication number: 20250006278Abstract: The memory device includes a plurality of memory cells which are arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasing operation. The memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. The circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.Type: ApplicationFiled: August 8, 2023Publication date: January 2, 2025Applicant: Western Digital Technologies, Inc.Inventors: Henry Chin, Hua-Ling Hsu, Yanwei He, Dong-II Moon
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Publication number: 20240428871Abstract: A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.Type: ApplicationFiled: August 3, 2023Publication date: December 26, 2024Applicant: Western Digital Technologies, Inc.Inventors: Kyeongran Yoo, Henry Chin, Hua-Ling Hsu, Yanwei He
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Publication number: 20240282392Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. The shared transfer data latch can be used to transfer data for operations being performed on a first plane to use the data latches on the other plane for storing data for operations on the first plane.Type: ApplicationFiled: July 3, 2023Publication date: August 22, 2024Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Frank Wanfang Tsai
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Patent number: 12057188Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: May 12, 2022Date of Patent: August 6, 2024Assignee: Sandisk Technologies, Inc.Inventors: Siddarth Naga Murty Bassa, YenLung Li, Hua-Ling Cynthia Hsu
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Publication number: 20240221803Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.Type: ApplicationFiled: July 27, 2023Publication date: July 4, 2024Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Victor Avila, Henry Chin
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Patent number: 12009049Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.Type: GrantFiled: August 31, 2022Date of Patent: June 11, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li, Siddarth Naga Murty Bassa, Jeongduk Sohn
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Ultra-large horizontal seepage test system with intelligent graded loading and variable seepage path
Patent number: 12000135Abstract: An ultra-large horizontal seepage test system with intelligent graded loading and variable seepage path is provided, which includes a water storage system, a water pressure system, a horizontal seepage test system and an intelligent loading and control system. The water storage system, the water pressure system and the horizontal seepage test system are connected in sequence, and the water pressure system is used to apply a water pressure and a vertical pressure to a test piece to be tested in the horizontal seepage test system. An outlet valve of the horizontal seepage test system is connected to the water storage system, and the intelligent loading and control system is used to control operations of electrical components of the water pressure system and the horizontal seepage test system. With the test system, a water head pressure can be loaded intelligently, and an infiltration angle of water inflow can be adjusted.Type: GrantFiled: September 23, 2021Date of Patent: June 4, 2024Assignee: NANJING HYDRAULIC RESEARCH INSTITUTEInventors: Beixiao Shi, Shengshui Chen, Hua Ling, Jianwei Zhang, Guangze Shen, Hua Fu, Huaqiang Han, Weiwei Xu -
Patent number: 11971829Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.Type: GrantFiled: December 21, 2021Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Patent number: 11971826Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.Type: GrantFiled: December 21, 2021Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Patent number: 11966621Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.Type: GrantFiled: February 17, 2022Date of Patent: April 23, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Aaron Lee
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Patent number: 11935599Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.Type: GrantFiled: April 21, 2022Date of Patent: March 19, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Hua-Ling Cynthia Hsu, Fanglin Zhang, Victor Avila
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Publication number: 20240071482Abstract: Technology is disclosed herein for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify. The lockout verify saves considerable current and/or power. However, performing the lockout verify during the first programming phase may slow performance due to a need to scan the content in a remote set of data latches.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Hua-Ling Cynthia Hsu
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Publication number: 20240071433Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li, Siddarth Naga Murty Bassa, Jeongduk Sohn
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Patent number: 11907545Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: April 28, 2022Date of Patent: February 20, 2024Assignee: SanDisk Technologies LLCInventors: YenLung Li, Siddarth Naga Murty Bassa, Chen Chen, Hua-Ling Cynthia Hsu
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Patent number: 11901019Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: February 8, 2022Date of Patent: February 13, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Masaaki Higashitani, YenLung Li, Chen Chen