Patents by Inventor Hua-Ling Hsu
Hua-Ling Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230410921Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
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Patent number: 11605436Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.Type: GrantFiled: June 21, 2021Date of Patent: March 14, 2023Assignee: SanDisk Technologies LLCInventors: Henry Chin, Hua-Ling Hsu, Liang Li, Xuan Tian, Fanglin Zhang, Guanhua Yin
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Publication number: 20220399061Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.Type: ApplicationFiled: June 21, 2021Publication date: December 15, 2022Applicant: SanDisk Technologies LLCInventors: Henry Chin, Hua-Ling Hsu, Liang Li, Xuan Tian, Fanglin Zhang, Guanhua Yin
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Publication number: 20220392551Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Applicant: SanDisk Technologies LLCInventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
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Patent number: 11521691Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.Type: GrantFiled: June 2, 2021Date of Patent: December 6, 2022Assignee: SanDisk Technologies LLCInventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
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Patent number: 11521686Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.Type: GrantFiled: March 31, 2021Date of Patent: December 6, 2022Assignee: SanDisk Technologies LLCInventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng, Fanglin Zhang
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Patent number: 11514991Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.Type: GrantFiled: May 4, 2021Date of Patent: November 29, 2022Assignee: SanDisk Technologies LLCInventors: Fanqi Wu, Hua-Ling Hsu, Deepanshu Dutta, Huai-yuan Tseng
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Publication number: 20220359023Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Applicant: SanDisk Technologies LLCInventors: Fanqi Wu, Hua-Ling Hsu, Deepanshu Dutta, Huai-yuan Tseng
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Publication number: 20220319605Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: SanDisk Technologies LLCInventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng, Fanglin Zhang
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Publication number: 20210407596Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: SanDisk Technologies LLCInventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng
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Patent number: 11211127Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.Type: GrantFiled: June 26, 2020Date of Patent: December 28, 2021Assignee: SanDisk Technologies LLCInventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng
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Patent number: 9899077Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.Type: GrantFiled: May 8, 2017Date of Patent: February 20, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Cynthia Hua-Ling Hsu, Aaron Lee, Abhijeet Manohar, Deepanshu Dutta
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Publication number: 20170243638Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.Type: ApplicationFiled: May 8, 2017Publication date: August 24, 2017Inventors: Cynthia Hua-Ling Hsu, Aaron Lee, Abhijeet Manohar, Deepanshu Dutta
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Patent number: 9653154Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.Type: GrantFiled: September 21, 2015Date of Patent: May 16, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Cynthia Hua-Ling Hsu, Aaron Lee, Abhijeet Manohar, Deepanshu Dutta
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Publication number: 20170084328Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.Type: ApplicationFiled: September 21, 2015Publication date: March 23, 2017Inventors: Cynthia Hua-Ling Hsu, Aaron Lee, Abhijeet Manohar, Deepanshu Dutta
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Patent number: 9530517Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.Type: GrantFiled: May 20, 2015Date of Patent: December 27, 2016Assignee: SanDisk Technologies LLCInventors: Aaron Lee, Zhenming Zhou, Mrinal Kochar, Cynthia Hua-Ling Hsu
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Publication number: 20160343449Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.Type: ApplicationFiled: May 20, 2015Publication date: November 24, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Aaron Lee, Zhenming Zhou, Mrinal Kochar, Cynthia Hua-Ling Hsu
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Patent number: 8456915Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.Type: GrantFiled: March 30, 2012Date of Patent: June 4, 2013Assignee: SanDisk Technologies Inc.Inventors: Changyuan Chen, Jeffrey Lutze, Yingda Dong, Hua-Ling Hsu
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Publication number: 20120188824Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Inventors: Changyuan Chen, Jeffrey Lutze, Yingda Dong, Hua-Ling Hsu
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Patent number: RE46056Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.Type: GrantFiled: March 31, 2014Date of Patent: July 5, 2016Assignee: SanDisk Technologies LLCInventors: Changyuan Chen, Jeffrey Lutze, Yingda Dong, Hua-Ling Hsu