Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Abstract: A silicone composition comprising (A) an electrically conductive filler, (B) a polydiorganosiloxane polymer, (C) a polyorganohydrogensiloxane, (D) a hydrosilylation reaction catalyst, (E) a polymer additive, and optionally (F) a hydrosilylation reaction inhibitor has a low complex viscosity upon admixing and upon cure provides a high electrical conductivity and good electrical conductivity retention after heat aging.

Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: The present invention provides a compound of Formula (I) and pharmaceutical compositions comprising one or more said compounds, and methods for using said compounds for treating or preventing influenza. The compounds are cap-dependent endonuclease inhibitors.

Abstract: A detection method includes: determining process data of a new process; according to the process data of the new process, detecting, by a first production system, whether a wafer carrier type of the new process matches an acceptable level of a corresponding process step or not and whether the new process matches a flag of the corresponding process step or not; if not, determining that the process data does not pass the detection and outputting first detection information; or if the wafer carrier type of the new process matches the acceptable level of the corresponding process step and the new process matches the flag of the corresponding process step, detecting, by a second production system, if the second production system detects a mismatch, determining that the process data does not pass the detection and outputting second detection information.

Abstract: A purification method of fungal cell wall composition includes following steps: (1) taking a residue of a fungus fruiting body underwent extraction process for obtaining extract thereof, wherein the extract contains terpenoids, sterols, polysaccharides, or a combination thereof, and the residue contains the cell wall of the fruiting body; (2) placing the residue into an aqueous percarbonate solution to form a mixture liquid, which is reacted at a first temperature for decolorizing the residue, wherein the concentration of the aqueous percarbonate solution ranges from 5 to 20% (w/v), and the first temperature ranges from 15 to 40° C.; (3) after the decolorization process, raising the temperature of the mixture liquid to a second temperature for the mixture liquid to react, so as to digest and decompose the residue, wherein the second temperature ranges from 80 to 100° C.; and (4) filtering the treated mixture liquid to obtain a purified product.

Abstract: Provided herein are prognostic methods for determining median survival of subjects from a cancer such as a desmoplastic cancer, a fibrolytic cancer or a pancreatic ductal adenocarcinoma (PDAC) as well as methods for treating same.

Abstract: A film peeling method is disclosed to peel off a film covered on the surface of an object. The method includes the steps of: setting a fulcrum located at outer side of the object; setting a lift-off position on the film; and picking up the film from the lift-off position with the fulcrum as the axis, and applying a circular traction force with a variable radius on the film for peeling off the film from the object. The film peeling method can peel off the film covered on the surface of the object by different peeling stages, to reduce the peeling path and reduce the force required for peeling the film, thereby reducing the peeling time and improving the peeling efficiency.

Abstract: A purification method of fungal cell wall composition includes following steps: (1) taking a residue of a fungus fruiting body underwent extraction process for obtaining extract thereof, wherein the extract contains terpenoids, sterols, polysaccharides, or a combination thereof, and the residue contains the cell wall of the fruiting body; (2) placing the residue into an aqueous percarbonate solution to form a mixture liquid, which is reacted at a first temperature for decolorizing the residue, wherein the concentration of the aqueous percarbonate solution ranges from 5 to 20% (w/v), and the first temperature ranges from 15 to 40° C.; (3) after the decolorization process, raising the temperature of the mixture liquid to a second temperature for the mixture liquid to react, so as to digest and decompose the residue, wherein the second temperature ranges from 80 to 100° C.; and (4) filtering the treated mixture liquid to obtain a purified product.

Abstract: A transceiver module includes a housing, a circuit board and a pull member. The housing has a received space and a guiding slot. The circuit board is disposed in the received space. The pull member is connected to the housing, and the pull member has a plate-shaped structure and an engaging structure. The plate-shaped structure extends along a long axis, and the engaging structure has a first curved portion connected to the plate-shaped structure. The plate-shaped structure forms two notches, and the engaging structure is located between the two notches.

Abstract: A detection method includes: determining process data of a new process; according to the process data of the new process, detecting, by a first production system, whether a wafer carrier type of the new process matches an acceptable level of a corresponding process step or not and whether the new process matches a flag of the corresponding process step or not; if not, determining that the process data does not pass the detection and outputting first detection information; or if the wafer carrier type of the new process matches the acceptable level of the corresponding process step and the new process matches the flag of the corresponding process step, detecting, by a second production system, if the second production system detects a mismatch, determining that the process data does not pass the detection and outputting second detection information.

Abstract: Provided herein are methods and compositions for treating cancer through a combination of an inhibitor of macropinocytosis upregulation and an autophagy inhibitor. Also provided are methods and compositions for inducing cell death of cancer cells, and transgenic animal models regarding same.

Abstract: A DC-to-DC converter includes a first DC side, a second DC side, a first capacitor, a first switch circuit, a magnetic element circuit, a second switch circuit, and a second capacitor. The DC-to-DC converter is adapted for converting between a first DC voltage and a second DC voltage. The magnetic element circuit is electrically coupled to the first switch circuit, and includes a plurality of magnetically coupled windings and an inductor. An oscillating current flowing in the first switch circuit is generated by controlling the first switch circuit and the second switch circuit, and an oscillating frequency of the oscillating current is determined by the capacitance of the first capacitor and the inductance of the inductor in the magnetic element circuit, and the first switch circuit and the second switch circuit are switched at a specific region of a wave trough of the oscillating current.

Abstract: A control unit is provided. The control unit is configured to provide a control signal for controlling a power unit. The power unit includes a first positive voltage terminal, a second positive voltage terminal, a first negative voltage terminal, a second negative voltage terminal, and a switching element. The first negative voltage terminal and the second positive voltage terminal are coupled to each other in a short circuit manner. One terminal of the switching element is electrically connected to the first negative voltage terminal. The control unit is configured to: receive a pulse width modulation signal; receive a first power supply signal; receive a second positive voltage terminal signal; output a second power supply signal; and output the control signal for controlling the switching element to be turned on or turned off.