Abstract: A method for reducing frequency interference, and a communication satellite system. The method includes configuring the communication satellite system, determining a first range of areas in which a spatial isolation angle between the LEO satellite and the GEO satellite does not satisfy a minimum spatial isolation angle within service areas of the movable spot beams, enabling the movable spot beams to not enter the areas, and when the movable spot beams of the transmitting and receiving user antennas of multiple adjacent LEO satellites provide services to a same area, calculating a spatial isolation angles between the movable spot beams of the transmitting and receiving user antennas of any two adjacent LEO satellites, and in response to the spatial isolation angle not satisfying the minimum spatial isolation angle, assigning different sub-frequencies to the movable spot beams that do not satisfy the minimum spatial isolation angle.

Abstract: The present invention is directed to a composition containing: an emollient system containing esters chosen from dicaprylyl ether, isopropyl myristate, caprylic/capric triglyceride, and sorbitan trioleate; sunscreen actives; an oil-soluble film-former; and optionally, an aesthetic modifier, wherein the composition is clear in appearance both during and after its application onto a keratinous substrate, and alcohol-free.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

Abstract: The invention is a thermoelectric device fabricated by growing a single crystal AlInN semiconductor material on a substrate, and a method of fabricating same. In a preferred embodiment, the semiconductor material is AlInN grown on and lattice-matched to a GaN template on a sapphire substrate, and the growth is performed using metalorganic vapor phase epitaxy (MOVPE).

Abstract: Methods of forming condensed first layer and semiconductor structures formed from the methods are provided. The methods include, for instance providing at least one layer disposed over a substrate structure of a semiconductor structure, wherein the substrate structure includes an upper silicon region; and performing at least one oxidation process of the semiconductor structure, the at least one oxidation process reducing a thickness of the upper region, wherein the performing facilitates diffusing to form a condensed layer over the substrate structure.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed.

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: The present invention is directed to a composition containing: an emollient system containing esters chosen from dicaprylyl ether, isopropyl myristate, caprylic/capric triglyceride, and sorbitan trioleate; sunscreen actives; an oil-soluble film-former; and optionally, an aesthetic modifier, wherein the composition is clear in appearance both during and after its application onto a keratinous substrate, and alcohol-free.

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract: The present invention relates to a composition intended for protecting the skin and/or hair against ultraviolet radiation containing: (a) at least one photoprotective system capable of screening out UV radiation; and (b) water-insoluble polymeric porous particles in spherical form.

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract: An interactive method for recording and playing data is implemented using an interactive system including a recording and playing unit, a processing unit, an RFID reader, and a memory. The method includes: a) configuring the processing unit to receive a record/stop request signal; b) configuring the processing unit to determine whether to activate the RFID reader; c) configuring the processing unit to activate the RFID reader for RFID tag reading when the processing unit determines to activate the RFID reader in step b); d) configuring the RFID reader to read a first RFID tag and to send a first identification code to the processing unit; e) configuring the processing unit to control the recording and playing unit to record data so as to generate recorded data; and f) configuring the processing unit to store the recorded data in the memory using the first identification code as an index.