Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. This permits serial data to be read one row at a time as well as one column at a time.

Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.

Abstract: Disclosed is a novel device, named the Accordion Shift Register (A.S.R.) by virtue of an alternative expansion-compaction behavior of the digital data as it passes through the device.The A.S.R. provides an economical substitute for the conventional L1/L2 type Shift register used in a large scale integrated (LSI) logic structures known as the Level Sensitive Scan Design (LSSD). (See U.S. Pat. No. 3,783,254).