Abstract: A system for visualization and quantification of ultrasound imaging data according to embodiments of the present disclosure may include a display unit, and a processor communicatively coupled to the display unit and to an ultrasound imaging apparatus for generating an image from ultrasound data representative of a bodily structure and fluid flowing within the bodily structure. The processor may be configured to estimate axial and lateral velocity components of the fluid flowing within the bodily structure, determine a plurality of flow directions within the image based on the axial and lateral velocity components, differentially encode the flow directions based on flow direction angle to generate a flow direction map, and cause the display unit to concurrently display the image including the bodily structure overlaid with the flow direction map.

Abstract: The present disclosure describes ultrasound systems configured to enhance flow imaging and analysis by adaptively adjusting one or more imaging parameters in response to acquired flow measurements. Example systems can include an ultrasound transducer and one or more processors. Using the system components, mean flow velocity magnitude and acceleration can be determined within a target region during an acquisition phase, which may include a cardiac cycle. One or more adjusted flow imaging parameters, such as adjusted ensemble length, temporal smoothing filter length and/or step size, can be determined based on the acquired flow measurements to increase the signal quality of newly acquired ultrasound echo signals. The adjusted flow imaging parameters can then be applied by the ultrasound transducer during a second acquisition phase.

Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.

Abstract: A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench and a gettering site. The semiconductor layer and the insulating layer are disposed on the insulating base layer in sequence, and the isolation trench is disposed in the semiconductor layer and passes through the insulating layer. The isolation trench includes a first cross-section, a second cross-section and a third cross-section from top to bottom. The first cross-section is higher than the bottom surface of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and in contact with the isolation trench, and the vertex of the gettering site is lower than the second cross-section.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection is provided. A post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver. The output node is configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration. The operational amplifier is further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit. The current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: Systems and methods for increasing the speed with which a network device can process “heartbeat” packets that are transmitted between the network device and its peers to verify that the communication links between them are active, or to detect when the communication links go down (i.e., are inactive). Received heartbeat packets are processed primarily by a switching application specific integrated circuit (ASIC) rather than a CPU of the network device. The switching ASIC identifies heartbeat sessions corresponding to received heartbeat packets and resets aging timers for these sessions if the timers have not already expired. The reduced processing and faster timing mechanism of the switching ASIC enables the network device to accommodate spikes in the received packet rate.

Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: The present disclosure relates to an embedded product, a method of displaying the debugging information of the embedded product, and a computer readable medium. The embedded product comprises a general CLI library containing one or a plurality of CLI commands for the embedded product, wherein at least some commands in the general CLI library are mapped to a debugging GUI, and the embedded product further comprises: a memory having instructions stored thereon; a processor configured to execute the instructions stored on the memory to cause the processor to carry out the following operations: receiving a request for information about the embedded product in response to a click on a page element on the debugging GUI; obtaining the requested embedded product information from the general CLI library; and receiving the obtained information about the requested embedded product and displaying the information on the debugging GUI.

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.

Abstract: The present disclosure is related to an access point device, a method, an apparatus and a medium. The access point device comprises: a memory having instructions stored thereon; and a processor configured to execute the instructions stored on the memory to cause the access point device to perform the following: determining an unstable client device which is disconnected from the access point device repeatedly; determining a flap reason for the client device based on a disconnecting message between the access point device and the client device; and performing an operation corresponding to the flap reason to stop flapping.

Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: The present disclosure relates to trunking communication systems, servers, access networks, and trunking communication methods. One example system includes a trunking management server and an access network. The trunking management server includes a trunking call service control module and a connected trunking call media gateway module. The trunking call media gateway module is configured to receive service data sent through the access network by a trunking UE, and forward the service data according to a communication type of the service data for implementing user plane communication of the trunking UE. The trunking call service control module is configured to receive a communication request sent through the access network by a trunking UE, and perform call control and bearer management on the trunking UE according to a communication type of the communication request for implementing control plane communication of the trunking UE.

Abstract: A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.

Abstract: A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.