Abstract: A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: Systems and methods for increasing the speed with which a network device can process “heartbeat” packets that are transmitted between the network device and its peers to verify that the communication links between them are active, or to detect when the communication links go down (i.e., are inactive). Received heartbeat packets are processed primarily by a switching application specific integrated circuit (ASIC) rather than a CPU of the network device. The switching ASIC identifies heartbeat sessions corresponding to received heartbeat packets and resets aging timers for these sessions if the timers have not already expired. The reduced processing and faster timing mechanism of the switching ASIC enables the network device to accommodate spikes in the received packet rate.

Abstract: A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: A semiconductor device and a method for operating the semiconductor device are provided. The semiconductor device includes a calibration device, an adjustment device and a driver. The calibration device is configured to continuously generate a first signal including a first number of bits. The adjustment device is configured to continuously receive the first signal and generate a second signal according to the last two bits of the first signal The second signal includes a second number of bits, and the second number is different from the first number. The driver is electrically coupled to the adjustment device, wherein an output resistance of the driver is controllable in response to the second signal.

Abstract: An apparatus including an integrated reference electrode and a fluid dispenser is described. The reference electrode includes a body and a tip. The fluid dispenser at least partially surrounds the tip of the reference electrode and includes an inlet, a chamber, and an outlet. The fluid dispenser is configured to receive a fluid sample from the inlet to the chamber and form a droplet of the fluid sample through the outlet so that the droplet is in fluidic contact with the tip of the reference electrode and associated with a known potential determined by the reference electrode.

Abstract: A speaker includes a telescopic sound chamber, a first diaphragm, and a first piezoelectric vibrating element. The telescopic sound chamber has a box wall, a bottom layer, and a first opening. The telescopic sound chamber includes a plurality of telescopic sub-box layers sleeved on and connected to each other and decreasing in volume layer by layer. The telescopic sound chamber accommodates the smaller telescopic sub-box layer into the larger telescopic sub-box layer to reduce the volume of the telescopic sound chamber. The telescopic sound chamber moves the smaller telescopic sub-box layer away from the larger telescopic sub-box layer to increase the volume of the telescopic sound chamber. The first diaphragm is arranged on the box wall to cover the first opening. The speaker can improve the drawbacks of low-frequency range distortion and has the advantages of full audio, high volume, and smooth sound pressure.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A method of operating an integrated circuit includes using a first switching device to couple a bio-sensing device to a first signal path, generating, using the bio-sensing device, a bio-sensing signal on the first signal path in response to an electrical characteristic of a sensing film, using a second switching device to couple a temperature-sensing device to a second signal path, and generating, using the temperature-sensing device, a temperature-sensing signal on the second signal path in response to a temperature of the sensing film. The first and second switching devices, the bio-sensing device, the temperature-sensing device, and the sensing film are components of a sensing pixel of a plurality of sensing pixels of the integrated circuit.

Abstract: A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench and a gettering site. The semiconductor layer and the insulating layer are disposed on the insulating base layer in sequence, and the isolation trench is disposed in the semiconductor layer and passes through the insulating layer. The isolation trench includes a first cross-section, a second cross-section and a third cross-section from top to bottom. The first cross-section is higher than the bottom surface of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and in contact with the isolation trench, and the vertex of the gettering site is lower than the second cross-section.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection is provided. A post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver. The output node is configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration. The operational amplifier is further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit. The current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: Systems and methods for increasing the speed with which a network device can process “heartbeat” packets that are transmitted between the network device and its peers to verify that the communication links between them are active, or to detect when the communication links go down (i.e., are inactive). Received heartbeat packets are processed primarily by a switching application specific integrated circuit (ASIC) rather than a CPU of the network device. The switching ASIC identifies heartbeat sessions corresponding to received heartbeat packets and resets aging timers for these sessions if the timers have not already expired. The reduced processing and faster timing mechanism of the switching ASIC enables the network device to accommodate spikes in the received packet rate.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: The present disclosure relates to an embedded product, a method of displaying the debugging information of the embedded product, and a computer readable medium. The embedded product comprises a general CLI library containing one or a plurality of CLI commands for the embedded product, wherein at least some commands in the general CLI library are mapped to a debugging GUI, and the embedded product further comprises: a memory having instructions stored thereon; a processor configured to execute the instructions stored on the memory to cause the processor to carry out the following operations: receiving a request for information about the embedded product in response to a click on a page element on the debugging GUI; obtaining the requested embedded product information from the general CLI library; and receiving the obtained information about the requested embedded product and displaying the information on the debugging GUI.

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.