Patents by Inventor Hua Xue

Hua Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224248
    Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. When diced, the resulting semiconductor dies have portions of the corners removed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 11, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Chin-Tien Chiu, Jia Li, Dongpeng Xue, Huirong Zhang, Guocheng Zhong, Xiaohui Wang, Hua Tan
  • Patent number: 11452947
    Abstract: The disclosure relates to the technical field of toy vehicles, in particular to a pull back vehicle capable of switching travelling lines including a pull back vehicle chassis. The pull back vehicle chassis includes a driving gear box, driving wheel, a driving gear, a steering wheel shaft, steering wheels and a centering spring. The pull back vehicle chassis is fixedly installed with the driving gear box, the driving gear box is fixedly connected with a driving axle, the driving axle is fixedly connected with the driving gear, and the driving axle is fixedly connected with the driving wheel, and the pull back vehicle chassis is fixedly connected with the steering wheel shaft.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 27, 2022
    Inventor: Hua Xue
  • Publication number: 20220297019
    Abstract: The invention refers to a model car configured to travel on at least two different paths comprising one path and at least one other path, the model car comprising a) a car chassis (1) having at least three wheels (102, 105) rotatably mounted thereto and a tensionable spring mechanism (101) in a rotary connection to at least one of said wheels (102) for driving said at least one wheel (102), wherein the energy stored in said tensioned spring mechanism (101) is used to drive said at least one drivable wheel (102) and to propel said model car standing on a surface, b) at least one of said wheels (105) embodied as a steerable wheel articulated in respect to the car chassis (1) about a steering axis (104) wherein articulation of the at least one steerable wheel (105) is effected by means of a steering gear (3), c) a deflection mechanism (2) which is operatively connected to the spring mechanism (101) in such a way that part of the energy stored in the tensioned spring mechanism (101) is used to steer the at lea
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventor: Hua XUE
  • Publication number: 20220105438
    Abstract: The disclosure relates to the technical field of toy vehicles, in particular to a pull back vehicle capable of switching travelling lines including a pull back vehicle chassis. The pull back vehicle chassis includes a driving gear box, driving wheel, a driving gear, a steering wheel shaft, steering wheels and a centering spring. The pull back vehicle chassis is fixedly installed with the driving gear box, the driving gear box is fixedly connected with a driving axle, the driving axle is fixedly connected with the driving gear, and the driving axle is fixedly connected with the driving wheel, and the pull back vehicle chassis is fixedly connected with the steering wheel shaft.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 7, 2022
    Inventor: Hua XUE
  • Patent number: 11097491
    Abstract: A mask-based partition preheating device and method are provided. The device includes an overall heating light source and a local preheating light source. A substrate provided at a forming cylinder is configured to heat an underlying powder. A mask plate is provided between the local preheating light source and the overall heating light source. A powder material to be sintered is coated on a local preheating zone. The local preheating light source, the mask plate and the overall heating light source are all connected to a temperature controller. A temperature control probe and a thermal imager in a temperature monitor are disposed in a working chamber for detecting the temperature of the powder surface.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 24, 2021
    Assignee: Kontour(Xi'an) Medical Technology Co., Ltd.
    Inventors: Liren Hu, Feng Zhao, Chaoliang Jin, Zhibin Wang, Ruoyu Zhao, Kai Tie, Jingfeng Yang, Yuan Li, Dongdong Zhao, Hua Xue
  • Publication number: 20210252788
    Abstract: A mask-based partition preheating device and method are provided. The device includes an overall heating light source and a local preheating light source. A substrate provided at a forming cylinder is configured to heat an underlying powder. A mask plate is provided between the local preheating light source and the overall heating light source. A powder material to be sintered is coated on a local preheating zone. The local preheating light source, the mask plate and the overall heating light source are all connected to a temperature controller. A temperature control probe and a thermal imager in a temperature monitor are disposed in a working chamber for detecting the temperature of the powder surface.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 19, 2021
    Applicant: Kontour(Xi'an) Medical Technology Co., Ltd.
    Inventors: Liren HU, Feng ZHAO, Chaoliang JIN, Zhibin WANG, Ruoyu ZHAO, Kai TIE, Jingfeng YANG, Yuan LI, Dongdong ZHAO, Hua XUE
  • Patent number: 10334383
    Abstract: Provided are a method and device for improving sound quality of stereo sound and a terminal. The method includes: an original left channel signal and an original right channel signal are acquired; phases, frequency spectrums and amplitudes of the original left channel signal and original right channel signal are acquired; a left calibrated signal is acquired according to the phase, frequency spectrum and amplitude of the original left channel signal, and a right calibrated signal is acquired according to the phase, frequency spectrum and amplitude of the original right channel signal; the left calibrated signal and the original right channel signal are superposed to generate a final right channel output signal; the right calibrated signal and the original left channel signal are superposed to generate a final left channel output signal; the final right channel output signal and the final left channel output signal are combined to form a PCM signal.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: June 25, 2019
    Assignee: ZTE Corporation
    Inventors: Tao Sun, Jinjun Wang, Hua Xue
  • Publication number: 20170230774
    Abstract: Provided are a method and device for improving sound quality of stereo sound and a terminal. The method includes: an original left channel signal and an original right channel signal are acquired; phases, frequency spectrums and amplitudes of the original left channel signal and original right channel signal are acquired; a left calibrated signal is acquired according to the phase, frequency spectrum and amplitude of the original left channel signal, and a right calibrated signal is acquired according to the phase, frequency spectrum and amplitude of the original right channel signal; the left calibrated signal and the original right channel signal are superposed to generate a final right channel output signal; the right calibrated signal and the original left channel signal are superposed to generate a final left channel output signal; the final right channel output signal and the final left channel output signal are combined to form a PCM signal.
    Type: Application
    Filed: October 24, 2014
    Publication date: August 10, 2017
    Applicant: ZTE CORPORATION
    Inventors: Tao SUN, Jinjun WANG, Hua XUE
  • Patent number: 9576093
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: February 21, 2017
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Venkatesan Rajappan, Mohana Tandyala, Hua Xue
  • Patent number: 9449133
    Abstract: Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: September 20, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Hua Xue, Mohan Tandyala, Nilanjan Chatterjee, Venkatesan Rajappan
  • Publication number: 20150379164
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Venkatesan Rajappan, Mohana Tandyala, Hua Xue
  • Publication number: 20150324509
    Abstract: Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 12, 2015
    Applicant: Lattice Semiconductor Corporation
    Inventors: Hua Xue, Mohan Tandyala, Nilanjan Chatterjee, Venkatesen Rajappan
  • Publication number: 20120003419
    Abstract: The present invention discloses a conveniently-hung towel comprising a towel body (1) and a hanging body (2) which is arranged on the upper end of the towel body (1), wherein a buckling device which enables the upper end and the lower end of the hanging body to be buckled together, is arranged on the hanging body (2). The towel can be hung on various handles through the buckling device, such as an oven handle, a cross bar, or an annular towel support. The towel has the characteristics of convenient use, beautiful appearance, sanitation, and low manufacturing cost.
    Type: Application
    Filed: January 28, 2010
    Publication date: January 5, 2012
    Inventor: Hua Xue
  • Patent number: 7895555
    Abstract: Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: February 22, 2011
    Assignee: Lattice Semiconductor Corporation
    Inventors: Chris West, Mike Ray, Bertrand Leigh, Hua Xue, Ju Shen
  • Patent number: 7788620
    Abstract: Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: August 31, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Hua Xue, Bertrand Leigh, Ju Shen, Chris West, Mike Ray
  • Patent number: 7032203
    Abstract: An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 18, 2006
    Assignee: Lattice Semiconductor Corporation
    Inventors: Gilles Bosco, Hua Xue
  • Publication number: 20050091809
    Abstract: A security tag includes a tag body and an attaching pin for attaching the tag body to a protected article. The security tag further includes a locking mechanism for releasably preventing the attaching pin from being removed from the protected article. The locking mechanism is provided for mechanically or magnetically released the attaching pin for detaching the tag body from the article. In a preferred embodiment, the locking mechanism further includes a plurality of balls for tightly holding to the attaching pin for releasably preventing the attaching means from being removed from the article. In a preferred embodiment, the locking mechanism further includes a mechanical unlocking probe finger for applying a mechanical force to release the balls from the attaching pin whereby the attaching pin may be released and detached from the tag body.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 5, 2005
    Inventors: Hua Xue, Jianping Sun
  • Patent number: 6199192
    Abstract: A system and method for routing signals to function blocks of a programmable logic device (PLD) via an interconnect multiplexer (XMUX). All available paths from an interconnect multiplexer input resource to an interconnect multiplexer output resource are first identified. Signals are assigned to XMUX paths in order of number of fanouts to function blocks. The signal required by the most function blocks is assigned first. The costs of the XMUX paths relative to the signal to be assigned are determined, and the signal is assigned to the path having the least cost. The process is repeated until all the signals are assigned. A recovery method uses augmenting paths to assign signals if all the signals could not be assigned using least cost paths assignment.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: March 6, 2001
    Assignee: Xilinix, Inc.
    Inventors: Jose M. Marquez, Hua Xue
  • Patent number: 6091892
    Abstract: A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: July 18, 2000
    Assignee: Xilinx, Inc.
    Inventors: Hua Xue, David A. Harrison, Joshua M. Silver
  • Patent number: 5969539
    Abstract: An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for simultaneous product term exporting to both previous and subsequent macrocells.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: October 19, 1999
    Assignee: Xilinx, Inc.
    Inventors: Isaak Veytsman, Jeffrey H. Seltzer, Hua Xue