Abstract: The present disclosure provides compositions and related methods, e.g., for preparing immobilized nucleic acid nanostructures using compaction oligonucleotides. In some embodiments, rolling circle amplification reaction can be conducted with compaction oligonucleotides on-support or in-solution to generate concatemer molecules having multiple copies of a polynucleotide unit arranged in tandem. Each polynucleotide unit comprises a sequence-of-interest and at least one universal adaptor sequence that binds one end of a compaction oligonucleotide. The 5? and 3? regions of the compaction oligonucleotide can hybridize to the concatemer to pull together distal portions of the concatemer causing compaction of the concatemer to form a nanostructure. Nanostructures having tighter size and shape compared to concatemers generated in the absence of the compaction oligonucleotides.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Abstract: A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature.

Abstract: A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.