Abstract: An article support device has a pair of support platforms arranged symmetrically and opposite to each other. Each of the support platforms includes a support frame, a support plate disposed on a top of the support frame and having a horizontal support top surface, and at least one positioning block installed on the horizontal support top surface. The horizontal support top surfaces of the support plates are located at a same height position. The article is supported on the horizontal support top surfaces and positioned between the positioning blocks on the support plates. An accommodation space is defined between the support plates and the support frames, and an automated guided vehicle moves into the accommodation space. An article carried on the article support device is loadable onto the automatic guided vehicle or the article carried on the automatic guided vehicle is unloadable onto the article support device.

Abstract: A portable visual inspection apparatus comprises a box including a lower box portion and an upper box portion. The upper box portion defines a first accommodation space and is connected to the lower box portion such that is capable of being opened and closed. A visual inspection device is installed in the first accommodation space and is adapted to be switched between an expanded configuration in which the visual inspection device is at least partially expanded for photographing an image of an article, and a folded configuration in which the visual inspection device is at least partially folded for storage in the first accommodation space. A support platform is arranged in the lower box portion and defines an inspection area below the visual inspection device in the expanded configuration. The portable visual inspection apparatus is switchable between a use configuration and a transportation configuration.

Abstract: A digital input and output signal test platform includes a digital input signal circuit, a digital output signal circuit, and a digital signal interface circuit. The digital input signal circuit generates a plurality of digital input signals and displays the generated digital input signals. The digital output signal circuit receives a plurality of digital output signals and displays the received digital output signals. The digital signal interface circuit transmits the generated digital input signals to digital input ports of an electronic product under test, and transmits the digital output signals output from digital output ports of the electronic product to the digital output signal circuit.

Abstract: An article support device has a pair of support platforms arranged symmetrically and opposite to each other. Each of the support platforms includes a support frame, a support plate disposed on a top of the support frame and having a horizontal support top surface, and at least one positioning block installed on the horizontal support top surface. The horizontal support top surfaces of the support plates are located at a same height position. The article is supported on the horizontal support top surfaces and positioned between the positioning blocks on the support plates. An accommodation space is defined between the support plates and the support frames, and an automated guided vehicle moves into the accommodation space. An article carried on the article support device is loadable onto the automatic guided vehicle or the article carried on the automatic guided vehicle is unloadable onto the article support device.

Abstract: A method for processing a consensus request in a computer network comprises: determining a pending request set, the pending request set including one or more pending consensus requests; determining a number of subsets that are in a consensus stage, wherein the subsets comprise the pending consensus requests that are obtained from the pending request set; and when the number of subsets that are in the consensus stage is less than a preset concurrent number of the computer network, issuing a consensus proposal for a new subset to the computer network to cause the new subset to enter the consensus stage to process the pending consensus requests, wherein the preset concurrent number is an upper limit of the number of subsets that are permitted to be simultaneously in the consensus stage in the computer network.

Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.

Abstract: A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.

Abstract: A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

Abstract: A level shifter physical verification system identifies missing level shifters in a multi-voltage domain integrated circuit design. The system analyzes a physical layout design data file for design to identify domains and signals that cross domains, and connected nets of devices within the IC design having one or more missing level shifters.