Patents by Inventor Huafeng XIAO

Huafeng XIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11624782
    Abstract: A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 11, 2023
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Yunhao Xing, Huafeng Xiao, Peng Wang
  • Publication number: 20220099735
    Abstract: A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 31, 2022
    Inventors: Yunhao XING, Huafeng XIAO, Peng WANG
  • Patent number: 11128144
    Abstract: A grid access current control method without current sensor applicable to a grid-connected inverter relates to a system including a main circuit of the grid-connected inverter and a control circuit of the grid-connected inverter. The control circuit of the grid-connected inverter includes a grid access current open-loop control module and a PWM generation module; the grid access current open-loop control module includes a first proportional regulator, a second proportional regulator, a delayer, and an adder; input ends of the first proportional regulator and the second proportional regulator each are led out as an input end of a grid access current reference signal; and an output end of the first proportional regulator is connected to an input end of the adder; an output end of the second proportional regulator is connected to an input end of the delayer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 21, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Huafeng Xiao, Zheng Wang, Ming Cheng
  • Publication number: 20200220361
    Abstract: A grid access current control method without current sensor applicable to a grid-connected inverter relates to a system including a main circuit of the grid-connected inverter and a control circuit of the grid-connected inverter. The control circuit of the grid-connected inverter includes a grid access current open-loop control module and a PWM generation module; the grid access current open-loop control module includes a first proportional regulator, a second proportional regulator, a delayer, and an adder; input ends of the first proportional regulator and the second proportional regulator each are led out as an input end of a grid access current reference signal; and an output end of the first proportional regulator is connected to an input end of the adder; an output end of the second proportional regulator is connected to an input end of the delayer.
    Type: Application
    Filed: October 17, 2018
    Publication date: July 9, 2020
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Huafeng XIAO, Zheng WANG, Ming CHENG