Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

Abstract: A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

Abstract: A synchronous opening and closing structure and a backpack including the same are provided. The synchronous opening and closing structure includes: a first opening and closing structure including a first sliding member and a first tape assembly, wherein the first sliding member is slidably disposed on the first tape assembly so that the first tape assembly is in a closed state or in an open state; a second opening and closing structure including a second sliding member and a second tape assembly, wherein the second sliding member is slidably disposed on the second tape assembly so that the second tape assembly is in the closed state or in the open state; and a connecting structure including a connector connecting the first sliding member and the second sliding member, wherein the connector moves to a first direction and a second direction opposite to the first direction.

Abstract: An improved linear hybrid brushless servo motor is disclosed. The motor comprises a forcer and a platen. The forcer has a plurality of stacks, permanent magnets, and coils which form a three-phase motor. The platen has a low cost ferromagnetic steel plate. The stacks, permanent magnets and phase coils of the forcer are specially designed to have the optimal electromagnetic coupling between the forcer and platen to achieve a high force density servomotor. In one embodiment, two E-shaped stacks are used to physically couple two phases to substantially minimize the unexpected cogging force and force ripple. Three other forcer configurations which achieve a three-phase, highly cost effective and high force density linear hybrid brushless servo motor are also disclosed.

Abstract: The present invention provides a device and a method to enhance thrust load capacity in a rotor bearing system. The load-enhancing device comprises a stator and a rotor arranged in such as way as to achieve a magnetic thrust load capacity enhancement by employing a number of permanent magnets, which produce an attracting force of an expulsing force between the rotor and the stator.

Abstract: A system and method are provided for controlling a three-phased permanent magnet electric motor terminal voltages in relation to both changes in speed and torque of the permanent magnet electric motor, whereby phase currents are first rotated from a stationary frame to two decoupled current components in a rotor synchronous frame, which enable to derive a voltage along a quadrature axis and a voltage along a direct axis thereof, before rotating back the quadrature and direct axis voltages from the rotor synchronous frame to the stationary frame to yield the permanent magnet electric motor terminal voltages.

Abstract: An improved linear hybrid brushless servo motor is disclosed. The motor comprises a forcer and a platen. The forcer has a plurality of stacks, permanent magnets, and coils which form a three-phase motor. The platen has a low cost ferromagnetic steel plate. The stacks, permanent magnets and phase coils of the forcer are specially designed to have the optimal electromagnetic coupling between the forcer and platen to achieve a high force density servomotor. In one embodiment, two E-shaped stacks are used to physically couple two phases to substantially minimize the unexpected cogging force and force ripple. Three other forcer configurations which achieve a three-phase, highly cost effective and high force density linear hybrid brushless servo motor are also disclosed.

Abstract: A power control system (12) for an electric motor having at least one magnetic bearing includes a DC/DC converter (18) supplied from a DC link bus (179) connected to a main power supply (14), the bus (17) supplying power for the electric motor and for a bearing actuator the converter (18) provides low voltage DC power supplies for a motor controller (23), a bearing controller (24) and a supervisory controller (26), the later monitoring the main power supply and communicating with the motor controller (23) and bearing controller (24) so as to cause the motor to operate as a generator in the event of a failure of the main power supply (14) to thereby supply power to the DC link bus (17) to maintain operation of the magnetic bearing. Circuit switching components are connected to the motor winding and selectively switched in a manner causing current generated in the motor winding to flow in one direction into the DC link bus (17) only while the winding voltage is greater than that of the DC link bus (17).

Abstract: The present invention provides a device and a method to enhance thrust load capacity in a rotor-bearing system. The load-enhancing device comprises a stator and a rotor arranged in such as way as to achieve a magnetic thrust load capacity enhancement by employing a number of permanent magnets, which produce an attracting force or an expulsing force between the rotor and the stator.

Abstract: A system and method are provided for controlling a three-phased permanent magnet electric motor terminal voltages in relation to both changes in speed and torque of the permanent magnet electric motor, whereby phase currents are first rotated from a stationary frame to two decoupled current components in a rotor synchronous frame, which enable to derive a voltage along a quadrature axis and a voltage along a direct axis thereof, before rotating back the quadrature and direct axis voltages from the rotor synchronous frame to the stationary frame to yield the permanent magnet electric motor terminal voltages.

Abstract: An algorithm for dynamic provisioning of fail-over support in Generalized Multi-Protocol Label Switching (“GMPLS”) enabled networks is disclosed. A Fault-Tolerant Routing and Wavelength Assignment (“FT-RWA”) scheme uses a pseudo-dynamic mechanism to provide such fail-over support for the GMPLS networks. The FT-RWA scheme is capable of recovering from channel and link failures within the GMPLS network. When a channel failure occurs, some wavelength channels on the link fail. As a result, traffic on the affected light paths are switched to any unused and reserved wavelengths on the same link. If no wavelengths are available, the failure is perceived as a link failure. When a link failure occurs, all or part of the traffic is redirected to a neighboring node, designated as a “redirector”. The redirector node calculates alternate routes to the destination of that link and creates a light path on a suitable route when a failure occurs.

Abstract: An actuator assembly for positioning read/write heads above a data storage media comprises a pivotally mounted carriage arm assembly with a voice coil and a magnetic device having a plurality of poles for generating a magnetic field. The voice coil is positioned with its effective portions crossing through the magnetic field to generate at least one pair of driving forces in a direction substantially orthogonal to a seeking direction of the read/write heads. The carriage arm driven by said pair of forces has substantially no reacting force generated onto the pivot so that the servo bandwidth of the head positioning assembly can be improved and achieves a high degree of head positioning accuracy.

Abstract: A packet transmission system includes a mechanism for controling congestion (30, FIG. 2) in the transmission system by comparing, at each switching node of the system (52, FIG. 5), the traffic load at that node and the traffic loads at all immediately neighboring switching nodes. Such traffic loads can be measured by node buffer utilization, either discretely or continuously, and loading information exchanged by the use of messages between the switching nodes (42, 54). The packet transmission speed between any two adjacent switching nodes is then adjusted (47, 62) in response to the relative traffic loads so as to reduce the traffic incoming to the more congested node. The transmission speed is never reduced to zero, however, to insure that a mechanism remains in place to relieve congestion at every transmitting switching node.