Patents by Inventor Huai-Hsien Chiu
Huai-Hsien Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749679Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: GrantFiled: July 2, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
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Publication number: 20210335785Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
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Patent number: 11075199Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: GrantFiled: February 11, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
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Patent number: 11004747Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: GrantFiled: May 11, 2020Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Publication number: 20200273754Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Patent number: 10692769Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: GrantFiled: October 31, 2017Date of Patent: June 23, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Patent number: 10651090Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: GrantFiled: October 31, 2017Date of Patent: May 12, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Patent number: 10529862Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.Type: GrantFiled: January 20, 2017Date of Patent: January 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming Liang, Huai-Hsien Chiu, Yi-Shien Mor
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Publication number: 20190189614Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
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Publication number: 20190067112Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: ApplicationFiled: October 31, 2017Publication date: February 28, 2019Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Patent number: 10204905Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.Type: GrantFiled: June 23, 2017Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
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Publication number: 20180308842Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.Type: ApplicationFiled: June 23, 2017Publication date: October 25, 2018Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
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Publication number: 20180151739Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.Type: ApplicationFiled: January 20, 2017Publication date: May 31, 2018Inventors: Chia-Ming Liang, Huai-Hsien Chiu, Yi-Shien Mor