Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: An apparatus for performing capacitor amplification in an electronic device may include a first resistor and a second resistor that are connected in series and coupled between a set of input terminals of a receiver in the electronic device, a common mode capacitor having a first terminal coupled to a common mode terminal and having a second terminal, and an alternating current (AC)-coupled amplifier that is coupled between the common mode terminal and the second terminal of the common mode capacitor. The first resistor and the second resistor may be arranged for obtaining a common mode voltage at the common mode terminal between the first resistor and the second resistor. In addition, the common mode capacitor may be arranged for reducing a common mode return loss. Additionally, the AC-coupled amplifier may be arranged for performing capacitor amplification for the common mode capacitor.

Abstract: An apparatus for performing capacitor amplification in an electronic device may include a first resistor and a second resistor that are connected in series and coupled between a set of input terminals of a receiver in the electronic device, a common mode capacitor having a first terminal coupled to a common mode terminal and having a second terminal, and an alternating current (AC)-coupled amplifier that is coupled between the common mode terminal and the second terminal of the common mode capacitor. The first resistor and the second resistor may be arranged for obtaining a common mode voltage at the common mode terminal between the first resistor and the second resistor. In addition, the common mode capacitor may be arranged for reducing a common mode return loss. Additionally, the AC-coupled amplifier may be arranged for performing capacitor amplification for the common mode capacitor.

Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided.

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided.

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract: A termination circuit is provided. The termination circuit includes a first receiving terminal, a second receiving terminal, a first resistive device, a second resistive device, a third resistive device, a fourth resistive device and a first switch. The first receiving terminal receives a first data signal. The second receiving terminal receives a second data signal. The first resistive device is coupled between a supply voltage and the first receiving terminal. The second resistive device is coupled between the supply voltage and the second receiving terminal. The third resistive device is coupled between the first receiving terminal and a first node. The fourth resistive device is coupled between the second receiving terminal and the first node. The first switch is coupled between the supply voltage and the first node.

Abstract: A termination circuit is provided. The termination circuit includes a first receiving terminal, a second receiving terminal, a first resistive device, a second resistive device, a third resistive device, a fourth resistive device and a first switch. The first receiving terminal receives a first data signal. The second receiving terminal receives a second data signal. The first resistive device is coupled between a supply voltage and the first receiving terminal. The second resistive device is coupled between the supply voltage and the second receiving terminal. The third resistive device is coupled between the first receiving terminal and a first node. The fourth resistive device is coupled between the second receiving terminal and the first node. The first switch is coupled between the supply voltage and the first node.

Abstract: A connection unit utilized in detecting an electronic device, comprising a first detection board, a second detection board and a connection board. The first detection board comprises a first contact area. The second detection board comprises a second contact area. The connection board is electrically connected to the electronic device, and comprises a first signal contact area and a second signal contact area, wherein the connection board is selectively connected to the first detection board and the second detection board. When the connection board connects the first detection board, the first signal contact area is electrically connected to the first contact area. When the connection board connects the second detection board, the second signal contact area is electrically connected to the second contact area.

Abstract: A connection unit utilized in detecting an electronic device, comprising a first detection board, a second detection board and a connection board. The first detection board comprises a first contact area. The second detection board comprises a second contact area. The connection board is electrically connected to the electronic device, and comprises a first signal contact area and a second signal contact area, wherein the connection board is selectively connected to the first detection board and the second detection board. When the connection board connects the first detection board, the first signal contact area is electrically connected to the first contact area. When the connection board connects the second detection board, the second signal contact area is electrically connected to the second contact area.