Patents by Inventor Huai-Ter V. Chong

Huai-Ter V. Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for error capture and logging in computer systems
    Patent number: 7424653
    Abstract: Disclosed are systems and methods for logging errors comprising at least one register for storing header packet information, a controller operable to determine if a received packet of one or more packets forming an information communication comprises a header packet and to store the header packet in said at least one register, and error logging circuitry coupled to the register operable to create an error log entry using header information retrieved from the register when an error is detected with respect to any of the one or more packets of the information communication.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: September 9, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • Systems and methods controlling transaction draining for error recovery
    Patent number: 7373555
    Abstract: Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order queue, and issuing transactions not tracked by the out-of-order queue.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 13, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • System and method for determining transaction time-out
    Patent number: 7219268
    Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 15, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • Systems and methods controlling transaction draining for error recovery
    Publication number: 20040237005
    Abstract: Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order queue, and issuing transactions not tracked by the out-of-order queue.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 25, 2004
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • System and method for determining transaction time-out
    Publication number: 20040237006
    Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 25, 2004
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • System and method for error capture and logging in computer systems
    Publication number: 20040225948
    Abstract: Disclosed are systems and methods for logging errors comprising at least one register for storing header packet information, a controller operable to determine if a received packet of one or more packets forming an information communication comprises a header packet and to store the header packet in said at least one register, and error logging circuitry coupled to the register operable to create an error log entry using header information retrieved from the register when an error is detected with respect to any of the one or more packets of the information communication.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong