Patents by Inventor Huai-Tzu Chiang
Huai-Tzu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047554Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.Type: ApplicationFiled: August 30, 2022Publication date: February 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Huai-Tzu Chiang, Chuang-Han Hsieh, Kai-Lin Lee
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Publication number: 20240021702Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.Type: ApplicationFiled: August 11, 2022Publication date: January 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Huai-Tzu Chiang, Kai-Lin Lee
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Publication number: 20230402537Abstract: A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.Type: ApplicationFiled: July 13, 2022Publication date: December 14, 2023Applicant: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Kai Lin Lee, Zhi-Cheng Lee, Chuang-Han Hsieh
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Patent number: 11843046Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: GrantFiled: January 11, 2021Date of Patent: December 12, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Publication number: 20220271153Abstract: An HEMT includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer. A gate is disposed on the aluminum gallium nitride layer. The gate includes a P-type gallium nitride and a schottky contact layer. The P-type gallium nitride contacts the schottky contact layer, and a top surface of the P-type gallium nitride entirely overlaps a bottom surface of the schottky contact layer. A protective layer covers the aluminum gallium nitride layer and the gate. A source electrode is disposed at one side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A drain electrode is disposed at another side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A gate electrode is disposed directly on the gate, penetrates the protective layer and contacts the schottky contact layer.Type: ApplicationFiled: March 29, 2021Publication date: August 25, 2022Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Yi-Chun Chan
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Publication number: 20210134994Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: ApplicationFiled: January 11, 2021Publication date: May 6, 2021Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Patent number: 10923586Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: GrantFiled: July 24, 2019Date of Patent: February 16, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Publication number: 20210020767Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: ApplicationFiled: July 24, 2019Publication date: January 21, 2021Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Publication number: 20200251583Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).Type: ApplicationFiled: March 6, 2019Publication date: August 6, 2020Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Patent number: 10714607Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).Type: GrantFiled: March 6, 2019Date of Patent: July 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Patent number: 10497797Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.Type: GrantFiled: November 16, 2015Date of Patent: December 3, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Kun-Hsin Chen, Tien-I Wu, Yu-Ru Yang, Huai-Tzu Chiang
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Patent number: 10439023Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: GrantFiled: July 19, 2018Date of Patent: October 8, 2019Assignee: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 10431652Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.Type: GrantFiled: December 7, 2017Date of Patent: October 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee
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Patent number: 10177231Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: GrantFiled: October 30, 2017Date of Patent: January 8, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20180323256Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Applicant: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 10068963Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: GrantFiled: November 9, 2015Date of Patent: September 4, 2018Assignee: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Publication number: 20180102411Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.Type: ApplicationFiled: December 7, 2017Publication date: April 12, 2018Inventors: Hsin-Yu Chen, Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee
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Publication number: 20180053826Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: ApplicationFiled: October 30, 2017Publication date: February 22, 2018Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Patent number: 9871102Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.Type: GrantFiled: April 13, 2015Date of Patent: January 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee
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Patent number: 9837493Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: GrantFiled: November 13, 2015Date of Patent: December 5, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu