Patents by Inventor Huaiqiang YU

Huaiqiang YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12244293
    Abstract: The disclosure provides a method for assembling and interconnecting FBAR filter and an electronic device. The method includes constructing an equivalent circuit model of an assembled FBAR filter according to a circuit model of a filter chip and the grounding circuit of the FBAR filter; modeling, simulating and calculating the grounding circuit to extract parasitic parameters corresponding to the grounding pad and a grounding bond-wire of the grounding circuit, respectively; feedbacking the parasitic parameters back into the equivalent circuit model, and using the circuit simulation software to obtain an S parameter of the filter; adjusting the parasitic parameters of the grounding circuit to optimize an S parameter performance of the FBAR filter: obtaining an optimal assembly configuration of the FBAR filter to guide the assembly. The parasitic parameters include a parasitic inductance of the grounding bond-wire and a parasitic capacitance and parasitic inductance of the grounding pad.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 4, 2025
    Assignee: NO. 26 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Huaiqiang Yu, Lei Zhang, Like Deng, Xi Wang, Bin Cheng, Jinyi Ma, Chuangxin Jiang, Mingyan Jiang, Shiyi Jiang, Meirui Liu, Xiao Peng
  • Publication number: 20240291496
    Abstract: A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher.
    Type: Application
    Filed: December 27, 2023
    Publication date: August 29, 2024
    Applicant: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 24 RESEARCH INSTITUTE
    Inventors: Ting LI, Ruzhang LI, Yong ZHANG, Yabo NI, Liang LI, Huaiqiang YU, Chao CHEN, Dongbing FU, Jianan WANG, Guangbing CHEN
  • Publication number: 20240223202
    Abstract: A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 4, 2024
    Applicant: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 24 RESEARCH INSTITUTE
    Inventors: Ting LI, Ruzhang LI, Yong ZHANG, Yabo NI, Chao CHEN, Liang LI, Huaiqiang YU, Dongbing FU, Jianan WANG, Guangbing CHEN
  • Publication number: 20230030644
    Abstract: The disclosure provides a method for assembling and interconnecting FBAR filter and an electronic device. The method includes constructing an equivalent circuit model of an assembled FBAR filter according to a circuit model of a filter chip and the grounding circuit of the FBAR filter; modeling, simulating and calculating the grounding circuit to extract parasitic parameters corresponding to the grounding pad and a grounding bond-wire of the grounding circuit, respectively; feedbacking the parasitic parameters back into the equivalent circuit model, and using the circuit simulation software to obtain an S parameter of the filter; adjusting the parasitic parameters of the grounding circuit to optimize an S parameter performance of the FBAR filter: obtaining an optimal assembly configuration of the FBAR filter to guide the assembly. The parasitic parameters include a parasitic inductance of the grounding bond-wire and a parasitic capacitance and parasitic inductance of the grounding pad.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 2, 2023
    Applicant: NO. 26 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Huaiqiang YU, Lei ZHANG, Like DENG, Xi WANG, Bin CHENG, Jinyi MA, Chuangxin JIANG, Mingyan JIANG, Shiyi JIANG, Meirui LIU, Xiao PENG