Abstract: An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values.

Abstract: Generating of the initial temperature value for a simulated annealing process in the placement of circuit components in the physical design of integrated circuit (IC) is based on previous partitioning, if any, of the IC components into bins. An iteration limit value is then assigned equal to the initial temperature value. The simulated annealing process is then performed on a current partitioning of the IC components into bins according to the iteration limit value. The IC components are partitioned further into an exponentially larger total number of smaller bins compared to a previous number of bins. The process is then repeated starting with the operation of generating an initial temperature value for the simulated annealing process until the number of circuit components in each bin is below a specified number.

Abstract: Generating of the initial temperature value for a simulated annealing process in the placement of circuit components in the physical design of integrated circuit (IC) is based on previous partitioning, if any, of the IC components into bins. An iteration limit value is then assigned equal to the initial temperature value. The simulated annealing process is then performed on a current partitioning of the IC components into bins according to the iteration limit value. The IC components are partitioned further into an exponentially larger total number of smaller bins compared to a previous number of bins. The process is then repeated starting with the operation of generating an initial temperature value for the simulated annealing process until the number of circuit components in each bin is below a specified number.