Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.

Abstract: A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

Abstract: A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.

Abstract: A signal converting device includes: a reference signal-mixing circuit arranged to generate a reference mixing output signal according to an input signal, a reference gain, and a reference local oscillating signal; a plurality of auxiliary signal-mixing circuits, each arranged to generate an auxiliary mixing output signal according to the input signal, an auxiliary gain, and an auxiliary local oscillating signal; and a combining circuit arranged to combine the reference mixing output signal and a plurality of the auxiliary mixing output signals to generate an output signal, and at least one of the auxiliary signal-mixing circuits is configured by the corresponding auxiliary gain to compensate phase imbalances between the reference mixing output signal and each of the auxiliary mixing output signals to reduce a power of a harmonic component in the output signal.

Abstract: A signal converting device includes: a reference signal-mixing circuit arranged to generate a reference mixing output signal according to an input signal, a reference gain, and a reference local oscillating signal; a plurality of auxiliary signal-mixing circuits, each arranged to generate an auxiliary mixing output signal according to the input signal, an auxiliary gain, and an auxiliary local oscillating signal; and a combining circuit arranged to combine the reference mixing output signal and a plurality of the auxiliary mixing output signals to generate an output signal, and at least one of the auxiliary signal-mixing circuits is configured by the corresponding auxiliary gain to compensate phase imbalances between the reference mixing output signal and each of the auxiliary mixing output signals to reduce a power of a harmonic component in the output signal.