Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Abstract: A method of patterning a dielectric layer with a Zep 520 positive EB photoresist as a mask, comprising the steps of depositing an ?-Si film on the dielectric layer; providing a layer of Zep 520 positive EB photoresist having high-resolution patterns therein by electron beam direct writing; etching the ?-Si film by chlorine-based plasma with the layer of Zep 520 positive EB photoresist as a mask, so as to transfer the high-resolution patterns of the Zep 520 positive EB photoresist to the underlying ?-Si film; removing the Zep 520 positive EB photoresist; etching the dielectric layer by fluorine-based plasma with the ?-Si film having high-fidelity patterns as a hard mask, so as to provide patterns of recesses; and removing the ?-Si film by wet etching or dry etching. The inventive method is completely compatible with and easily incorporated into the conventional CMOS processes, with high reliability and resolution for providing nanoscale fine patterns of recesses.

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: The present application discloses a method for manufacturing a full silicidation metal gate, comprises the steps of forming locally oxidized isolation or shallow trench isolation, performing prior-implantation oxidation and then doping 14N+; removing the prior-implantation oxidation layer formed before ion implantation, performing gate oxidation, and depositing a polysilicon layer; performing lithography and etching to form a gate electrode of polysilicon; implanting and activating dopants; depositing metal such as Ni; performing a first annealing so that Ni reacts with a portion of polysilicon; selectively removing unreacted Ni; performing a second annealing so that the whole gate electrode is converted into nickel silicide to form a full silicidation metal gate electrode. The present invention provides a full silicidation metal gate electrode which overcomes the disadvantages of polysilicon gate electrode.

Abstract: A method of patterning a dielectric layer with a Zep 520 positive EB photoresist as a mask, comprising the steps of depositing an ?-Si film on the dielectric layer; providing a layer of Zep 520 positive EB photoresist having high-resolution patterns therein by electron beam direct writing; etching the ?-Si film by chlorine-based plasma with the layer of Zep 520 positive EB photoresist as a mask, so as to transfer the high-resolution patterns of the Zep 520 positive EB photoresist to the underlying ?-Si film; removing the Zep 520 positive EB photoresist; etching the dielectric layer by fluorine-based plasma with the ?-Si film having high-fidelity patterns as a hard mask, so as to provide patterns of recesses; and removing the ?-Si film by wet etching or dry etching. The inventive method is completely compatible with and easily incorporated into the conventional CMOS processes, with high reliability and resolution for providing nanoscale fine patterns of recesses.

Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.

Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.