Abstract: The preset application discloses a task scheduling method, including: in response to receiving an issued task, dividing, by a parser, the task into sub-tasks and generating a sub-task list, a task parameter corresponding to each sub-task is recorded in the sub-task list, the task parameter includes a start phase of a next sub-task; sending, by a scheduler, the task parameter of a sub-task to be processed in the sub-task list to a corresponding sub-engine; executing, by the corresponding sub-engine, a corresponding sub-task to be processed; sending a notification to the scheduler in response to an operating phase when the corresponding sub-engine executes the corresponding sub-task to be processed being the same as the start phase in the received task parameter; and in response to the notification being detected by the scheduler, returning to the step of sending the task parameter of a sub-task to be processed to a corresponding sub-engine.

Abstract: A method for processing data overflow in a decompression process, includes: decompressing an original text, and detecting whether a data overflow event occurs in the decompression process; in response to detecting the data overflow event, storing first data obtained by decompression in a host cache into a target memory, and closing a data read-in port of a decoding engine; decompressing data which is being decompressed in the decoding engine to obtain second data, and storing the second data into a cache of the decoding engine; calculating a position of the decompressed data in the original text; obtaining, on the basis of the position, data which is not decompressed in the original text, re-decompressing the data which is not decompressed to obtain third data, and storing the second data into the target memory; and splicing the first data, the second data, and the third data to obtain complete decompressed data.

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.