Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

Abstract: A manufacturing method for a super-? bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.

Abstract: Provided is a nucleic acid construct, including the following elements: a transposon 3? terminal repeat, first poly A sequence, an insulator sequence having a transcription termination function, a transposon 5? terminal repeat, a transposase coding sequence, and a promoter that controls the expression of the transposase. Also provided are a host cell or pharmaceutical composition including said nucleic acid construct, and a use thereof.

Abstract: A seed cell medium of a tumor-infiltrating lymphocyte and an application thereof. The medium contains a cell culture component, a cell factor, and an immune checkpoint antibody or an antigen-binding fragment thereof. The cell factor includes IL-2; an immune checkpoint includes PD-1, LAG-3, TIGIT, and/or CTLA-4; and the cell culture component is a serum medium or a serum-free medium. The seed cell medium accelerates a culture of a seed cell of the tumor-infiltrating lymphocyte and shortens the amplification time required by the tumor-infiltrating lymphocyte.

Abstract: A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

Abstract: A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

Abstract: The invention relates to a T cell expressing an antibody or comprising the coding sequence of the antibody or an expression vector thereof; the antibody contains an optional signal peptide, an antigen binding sequence and a mutant type Fc segment, wherein the mutant type Fc segment is a Fc segment in which amino acid residues at the 17th site and the 79th site of the IgG4 Fc segment shown by SEQ ID NO: 25 are mutated into E and Q respectively. Preferably, the T cell is a CAR-T cell. The present invention further relates to a treatment application of the T cell in malignant tumors.

Abstract: Provided are a dual-activating costimulatory molecule receptor and the use thereof. The dual-activating costimulatory molecule receptor comprises the following elements from the N-terminus to the C-terminus: a selectable signal peptide, a costimulatory signal molecule-activating single-chain antibody, an extracellular hinge area, a transmembrane region and an intracellular costimulatory signal molecule. The dual-activating costimulatory molecule receptor can produce a strong clustering effect when co-modifying T-cells with first-generation CAR-T comprising a first signal, can kill tumor cells, and at the same time, does not trigger a strong T-cell immunity or cause potentially serious toxic side effects.

Abstract: Provided is a chimeric promoter with a high transcriptional activity in T-cells. The chimeric promoter consists of an enhancer sDTS and a promoter operably linked to the enhancer. The sequence of the enhancer is as shown in SEQ ID NO: 1. The enhancer is located at the 5? or 3? terminus of the promoter. Also provided are nucleic acid constructs, vectors and T-cells comprising the chimeric promoter. The chimeric promoter can drive the efficient expression of exogenous genes in T-cells.

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall

Abstract: Provided is a transgenic killer cell, the genome of which is stably integrated with a coding sequence comprising an antibody of a human Fc section, or an expression cassette of a coding sequence comprising a chimeric antigen receptor or an inhibitory or agonistic antibody, and an inverted terminal repeat sequence from a transposon at both ends. Also provided is a pharmaceutical composition comprising the transgenic killer cell, and uses thereof.

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.