Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer.

Abstract: A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer.

Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.

Abstract: A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer.

Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.

Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.

Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.

Abstract: A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention, the dangling bonds between silicon oxide in a tunneling oxide layer and silicon adjacent to a semiconductor substrate interface are terminated by performing a annealing on a tunneling oxide layer, thereby improving the erase rate of the tunneling oxide layer.