Patents by Inventor Huaming Hu

Huaming Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip level scan chain planning for hierarchical design flows
    Patent number: 7657850
    Abstract: A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: February 2, 2010
    Assignee: Synopsys, Inc.
    Inventors: Lin Huang, Huaming Hu
  • Chip level scan chain planning for hierarchical design flows
    Publication number: 20080141086
    Abstract: A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Applicant: Synopsys, Inc.
    Inventors: Lin Huang, Huaming Hu