Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A multi-level over-current protection circuit includes: a signal amplification circuit configured to receive a set of detection signals and output a first signal; a comparison circuit to compare the first signal with a first reference signal and a second reference signal respectively; and a time delay counting circuit. The time delay counting circuit adjusts a first count value when the first signal is higher than or equal to the first reference signal and smaller than the second reference signal, and the time delay counting circuit activates a protection mode when the first count value reaches a first protection time delay. The time delay counting circuit adjusts a second count value when the first signal is higher or equal to the second reference signal, and activates the protection mode when the second count value reaches a second protection time delay.

Abstract: A multi-level over-current protection circuit includes: a signal amplification circuit configured to receive a set of detection signals and output a first signal; a comparison circuit to compare the first signal with a first reference signal and a second reference signal respectively; and a time delay counting circuit. The time delay counting circuit adjusts a first count value when the first signal is higher than or equal to the first reference signal and smaller than the second reference signal, and the time delay counting circuit activates a protection mode when the first count value reaches a first protection time delay. The time delay counting circuit adjusts a second count value when the first signal is higher or equal to the second reference signal, and activates the protection mode when the second count value reaches a second protection time delay.

Abstract: The present disclosure provides a single-phase three-wire power control system integrating the electricity of a DC power supply device to an AC power source. The single-phase three-wire power control system comprises a single-phase three-wire inverter, a driving unit, a sampling unit and a processing unit. The single-phase three-wire inverter coupled between the DC power supply device and the AC power source converts a DC voltage of the DC power supply device to an output voltage. The driving unit is coupled to the single-phase three-wire inverter. The sampling unit samples the inductor current of an inductor of the single-phase three-wire inverter. The processing unit which is coupled to the driving unit and the sampling unit controls the single-phase three-wire inverter through the driving unit. The processing unit obtains the duty ratio according to the inductance of the inductor, the total variation of the inductor current, the DC voltage and the output voltage.

Abstract: The present disclosure provides a single-phase three-wire power control system integrating the electricity of a DC power supply device to an AC power source. The single-phase three-wire power control system comprises a single-phase three-wire inverter, a driving unit, a sampling unit and a processing unit. The single-phase three-wire inverter coupled between the DC power supply device and the AC power source converts a DC voltage of the DC power supply device to an output voltage. The driving unit is coupled to the single-phase three-wire inverter. The sampling unit samples the inductor current of an inductor of the single-phase three-wire inverter. The processing unit which is coupled to the driving unit and the sampling unit controls the single-phase three-wire inverter through the driving unit. The processing unit obtains the duty ratio according to the inductance of the inductor, the total variation of the inductor current, the DC voltage and the output voltage.